IP Library Granted Patent US 7,847,299
Granted Patent B2
US 7,847,299 · App. 11/964,519 · Granted Dec 7, 2010

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 7,847,299
App. No.
11/964,519
Granted
Dec 7, 2010
Kind
B2
Abstract

The invention provides a semiconductor device with high reliability and smaller size and a method of manufacturing the same. A light emitting element as a device element is formed on the front surface of a semiconductor substrate, for example. In detail, an N-type semiconductor layer, a P-type semiconductor layer and pad electrodes are formed on the front surface of the semiconductor substrate. A device element receiving light from the light emitting element (e.g. a photodiode element), for example, and pad electrodes are formed on the front surface of another semiconductor substrate. The semiconductor substrates are attached and integrated with an adhesive layer being interposed therebetween. Wiring layers electrically connected to the pad electrodes and wiring layers electrically connected to the other pad electrodes are formed on the side surface of the semiconductor substrate.

Claims (15)

1. A semiconductor device, comprising:

a first substrate comprising a first device element formed on a front surface thereof;

a second substrate comprising a second device element formed on a front surface thereof;

a first pad electrode disposed on the front surface of the first substrate and electrically connected to the first device element;

a second pad electrode disposed on the front surface of the second substrate and electrically connected to the second device element; and

an adhesive layer disposed between the front surface of the first substrate and the front surface of the second substrate so that the first and second substrates are adhered together to form an integrated die,

wherein, in plan view of the semiconductor device, the first pad electrode does not overlap any pad electrode formed on the front surface of the second substrate, and the second pad electrode does not overlap any pad electrode formed on the front surface of the first substrate.

2. The semiconductor device of claim 1 , further comprising a first conductive terminal electrically connected to the first pad electrode and a second conductive terminal electrically connected to the second pad electrode, the first and the second conductive terminals extending in a direction normal to the front surfaces of the first and second substrates.

3. The semiconductor device of claim 1 , further comprising a first wiring layer electrically connected to the first pad electrode and a second wiring layer electrically connected to the second pad electrode, the first and the second wiring layers being disposed on side surfaces of the second substrate.

4. The semiconductor device of claim 3 , wherein the first and the second wiring layers extend to cover a back surface of the second substrate.

5. The semiconductor device of claim 1 , further comprising penetration holes penetrating the second substrate and filled with a conductive member, the first and second pad electrodes being configured to be electrically connected to an external power supply through the filled penetration holes.

6. The semiconductor device of claim 1 , wherein part of the adhesive layer is removed above the first pad electrode so as to accommodate a conductive member for external power connection to the first pad electrode.

7. The semiconductor device of claim 1 , wherein the first device element comprises a light emitting element, and the second device element comprises a light receiving element receiving light from the light emitting element.

8. The semiconductor device of claim 1 , wherein the first device element or the second device element comprises a MEMS element.

9. The semiconductor device of claim 1 , wherein the first pad electrode is electrically separated from the second pad electrode.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2008
From: NOMA, TAKASHI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 020597/0934 →