Semiconductor memory device
View Patent ↗A semiconductor memory device comprises a memory cell array having a hierarchical word line structure including main word lines and sub-word lines; a main word driver for driving a non-selected main word line to high and for driving and activating a selected main word line to low; and a sub-word driver having a PMOS transistor whose gate is connected to the main word line for selectively activating the sub-word line corresponding to the selected main word line. The memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in the other area.
1. A semiconductor memory device comprising:
a memory cell array having a hierarchical word line structure including a plurality of main word lines and a plurality of sub-word lines;
a main word driver for driving a non-selected main word line to a high level and for driving and activating a selected main word line to a low level; and
a sub-word driver having at least a PMOS transistor to a gate of which the main word line is connected, said sub-word driver for selectively activating the sub-word line corresponding to the selected main word line,
wherein said memory cell array is divided into a plurality of areas which is controlled such that a high level of each main word line is set to a first boost voltage in a predetermined area including the selected main word line, and a high level of each main word line is set to a second boost voltage lower than the first boost voltage in each area other than the predetermined area.
2. The semiconductor memory device according to claim 1 further comprising a voltage switching circuit capable of selectively outputting the first boost voltage and the second boost voltage,
wherein the first boost voltages is supplied to said main word driver in the predetermined area, and the second boost voltage is supplied to said main word driver in each area other than the predetermined area.
3. The semiconductor memory device according to claim 2 , wherein the plurality of areas is a plurality of memory mats into which said memory cell array is divided for every predetermined number of the main word lines.
4. The semiconductor memory device according to claim 3 , wherein said voltage switching circuit is controlled such that the first and second boost voltages are selectively switched in response to a mat select signal for selecting the memory mat.
5. The semiconductor memory device according to claim 4 , wherein each of the memory mats is divided into a plurality of sub mats for every predetermined number of the main word lines, and each of the sub mats is arranged between sub-word driver groups each including a plurality of the sub-word drivers.
6. The semiconductor memory device according to claim 1 , wherein N (N is an integer equal to or greater than two) sub-word lines are formed corresponding to each of the main word lines, N sub-word drivers for activating the respective sub-word lines are provided, and one of the sub-word drivers is selectively driven in response to sub-word select signals different from one another.
7. The semiconductor memory device according to claim 6 further comprising a driver circuit for selectively activating N sub-word select signals supplied to the N sub-word drivers,
wherein one of the N sub-word select signals output from said driver circuit is coupled to one end of the PMOS transistor included in each of the sub-word drivers.