Delay cell and phase locked loop using the same
View Patent ↗A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
1. A delay cell, comprising:
a first current controller configured to supply first and second currents to first and second nodes in response to a control voltage;
a signal input unit configured to output differential output signals in response to differential input signals and in response to total currents flowing through the first and second nodes, respectively; and
a second current controller configured to selectively add third and fourth currents to the first and second nodes, respectively, in response to one or more frequency range selection signals,
wherein the second current controller receives a supply voltage, makes a current path between the supply voltage and the first and second nodes and generates the third and fourth currents in response to a predetermined bias voltage, which is different from the control voltage and the supply voltage, and supplies the third and fourth currents to the first and second nodes respectively depending on whether the one or more frequency range selection signals are activated or inactivated.
2. The delay cell of claim 1 , further comprising a loading unit configured between the signal input unit and a ground voltage terminal.
3. The delay cell of claim 1 , wherein the frequency range selection signals are skew information signals generated from a mode register set or a fuse option circuit.
4. The delay cell of claim 1 , wherein the frequency range selection signals correspond to process, voltage and temperature (PVT) information.
5. The delay cell of claim 1 , further comprising a band gap circuit configured to generate the predetermined bias voltage.
6. The delay cell of claim 5 , further comprising a capacitor connected between an output node of the band gap circuit and a supply voltage terminal for the first and second current controllers.
7. The delay cell of claim 1 , wherein the second current controller includes:
a first current supplying unit configured to supply the third current to the first node in response to the predetermined bias voltage and the frequency range selection signals; and
a second current supplying unit configured to supply the fourth current to the second node in response to the predetermined bias voltage and the frequency range selection signals.
8. The delay cell of claim 7 , wherein the first current supplying unit includes:
a current generator configured to generate the third current in response to the predetermined bias voltage; and
a current transmitter configured to transmit the third current to the first node in response to the frequency range selection signal.
9. The delay cell of claim 7 , wherein the second current supplying unit includes:
a current generator configured to generate the fourth current in response to the bias voltage; and
a current transmitter configured to transmit the fourth current to the second node in response to the frequency range selection signal.
10. The delay cell of claim 8 , wherein the current generator and the current transmitter are connected in series between the supply voltage and the first node.
11. The delay cell of claim 8 , wherein the current generator comprises a transistor having the predetermined bias voltage supplied to its gate terminal and the current transmitter comprises another transistor having one of the frequency range selection signals supplied to its gate terminal.
12. The delay cell of claim 9 , wherein the current generator and the current transmitter are connected in series between the supply voltage and the second node.
13. The delay cell of claim 9 , wherein the current generator comprises a transistor having the predetermined bias voltage supplied to its gate terminal and the current transmitter comprises another transistor having one of the frequency range selection signals supplied to its gate terminal.