Method for fabricating isolation layer in semiconductor device
View Patent ↗A method for fabricating an isolation layer in a semiconductor device includes providing a substrate, forming a trench over the substrate, forming a liner nitride layer and a liner oxide layer along a surface of the trench, forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer, forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer, and forming a high density plasma (HDP) oxide layer for filling the remaining a portion of the trench.
1. A method for fabricating an isolation layer in a semiconductor device, the method comprising:
providing a substrate;
forming a trench over the substrate;
forming a liner nitride layer and a liner oxide layer along a surface of the trench;
forming an insulation layer having an etch selectivity ratio different from that of the liner oxide layer over the liner oxide layer;
forming a spin on dielectric (SOD) oxide layer to fill a portion of the trench over the insulation layer; and
forming a high density plasma (HDP) oxide layer for filling the remaining portion of the trench.
2. The method of claim 1 , wherein the insulation layer includes a nitride layer and has a thickness ranging from approximately 20 Å to approximately 50 Å.
3. The method of claim 1 , wherein the insulation layer includes a silicon oxy-nitride (SiON) layer and has a thickness ranging from approximately 20 Å to approximately 100 Å.
4. The method of claim 1 , wherein the insulation layer includes a hafnium oxide (HfO 2 ) layer or an aluminum oxide (Al 2 O 3 ) layer and has a thickness ranging from approximately 20 Å to approximately 50 Å.
5. The method of claim 1 , wherein forming the SOD oxide layer includes:
forming the SOD oxide layer over the insulation layer until the trench is filled;
planarizing the SOD oxide layer to a top surface of the substrate; and
partially etching the SOD oxide layer to remain in the portion of the trench.
6. The method of claim 5 , wherein the planarization process is performed using a chemical mechanical polishing (CMP) method.
7. The method of claim 5 , wherein said partially etching the SOD oxide layer is performed through a wet etch using a buffered oxide etchant (BOE).
8. The method of claim 1 , wherein the liner oxide layer includes a low pressure tetra ortho silicate (LP-TEOS) layer and has a thickness ranging from approximately 20 Å to approximately 200 Å.
9. The method of claim 1 , wherein the liner oxide layer includes a plasma oxide layer and has a thickness ranging from approximately 20 Å to approximately 50 Å.
10. The method of claim 1 , further comprising, before forming the liner nitride layer, forming a thermal oxide layer along the surface of the trench.