Dummy cell for memory circuits
View Patent ↗A memory cell array includes reference cells each associated with a plurality of data cells of the array.
1. A memory cell array comprising:
a plurality of reference cells each associated with a plurality of data cells of the array;
logic to fatigue the reference cells by an amount proportional to a fatigue resulting from memory operations to the associated data cells; and
logic to apply one or more threshold voltage levels for reading the reference cells and to form at least one reference voltage for reading the data cells based upon the threshold levels for reading the reference cells.
2. The memory cell array of claim 1 , wherein the plurality of reference cells each associated with a plurality of data cells of the array further comprises:
at least one reference cell associated with each word line or part of a word line of data cells in the array.
3. The memory cell array of claim 2 , wherein the at least one reference cell associated with each word line or part of a word line of data cells in the array further comprises:
two reference cells associated with each word line or part of a word line of data cells in the array.
4. The memory cell array of claim 1 , wherein the logic to apply one or more threshold voltage levels for reading the reference cells and to form at least one reference voltage for reading the data cells based upon the threshold levels for reading the reference cells further comprises:
logic to apply a first threshold voltage level for reading a logical high value from the reference cells, to apply a second threshold voltage level for reading a logical low value from the reference cells, and to form a third reference voltage for reading the data cells based upon the first and second threshold voltage levels.
5. The memory cell array of claim 4 , wherein the logic to apply a first threshold voltage level for reading a logical high value from the reference cells, to apply a second threshold voltage level for reading a logical low value from the reference cells further comprises:
logic to adjust one or both of the first threshold voltage level and the second threshold voltage level when one or more of the values read from the reference cells are inaccurate.
6. The memory cell array of claim 1 , further comprising:
logic to apply memory operations to the reference cells in coordination with operations to corresponding data cells, so that fatigue of the reference cells is proportional to fatigue of the corresponding data cells.
7. The memory cell array of claim 6 , wherein the logic to apply memory operations to the reference cells in coordination with operations to corresponding data cells further comprises:
logic to invert the values stored in the reference cells with each write operation to the corresponding data cells.
8. The memory cell array of claim 1 , further comprising:
logic to validate values read from data cells when values read from corresponding reference cells are accurate, and to invalidate the values from the data cells otherwise.
9. A process for reading the values stored in electronic memory data cells, comprising:
applying at least one reference voltage to at least one reference cell associated with at least one data cells; and
forming a reference voltage for the at least one data cells from the reference voltage applied to the reference cell(s); and
applying a memory operation to a data cell; and
applying an operation to a reference cell corresponding to the data cell, the operation to the reference cell selected to fatigue the reference cell by an amount proportional to a fatigue to the data cell resulting from the memory operation;
reading values from the reference cells; and
invalidating values read from the data cells when the values read from the reference cells are not expected values.
10. The process of claim 9 , further comprising:
adjusting the at least one reference voltage to the reference cells when the values read from the reference cells are not expected values.
11. The process of claim 9 , further comprising:
applying a first threshold voltage level for reading a logical high value from the reference cells, and applying a second threshold voltage level for reading a logical low value from the reference cells.
12. The process of claim 9 , further comprising:
applying memory operations to the reference cells in coordination with operations to associated data cells, so that fatigue of the reference cells is proportional to fatigue of the associated data cells.
13. The process of claim 12 , further comprising:
inverting the values stored in the reference cells with each write operation to the associated data cells.
14. A device comprising:
at least one processor, and
a memory system, the memory system comprising a memory cell array, the array comprising a plurality of reference cells each associated with a plurality of data cells of the array; and
logic to fatigue the reference cells by an amount proportional to a fatigue resulting from memory operations to the associated data cells;
logic to apply one or more threshold voltage levels for reading the reference cells and to form at least one reference voltage for reading the data cells based upon the threshold levels for reading the reference cells.
15. The device of claim 14 , wherein the plurality of reference cells each associated with a plurality of data cells of the array further comprises:
at least one reference cell associated with each word line or part of a word line of data cells in the array.
16. The device of claim 15 , wherein the at least one reference cell associated with each word line of data cells in the array further comprises:
two reference cells associated with each word line of data cells in the array.
17. The device of claim 14 , further comprising:
logic to adjust one or both of a first threshold voltage level and a second threshold voltage level to the reference cells when one or more values read from the reference cells are inaccurate.