Delay circuit of semiconductor memory apparatus

1. A delay circuit of a semiconductor memory apparatus, comprising:

a clock period sensing unit for sensing frequency of an input clock to generate a sensing signal in response to sensed frequency of the input clock; and

a selective delay unit for delaying an input signal for a delay time and outputting the input signal as an output signal,

wherein the delay time is one selected from a plurality of delay times according to the sensing signal,

wherein the clock period sensing unit is initialized in response to a reset signal, and

wherein the clock period sensing unit is initialized when the reset signal is activated and generates the sensing signal after one period of the clock from inactivating the reset signal.

2. The delay circuit of claim 1 , wherein the clock period sensing unit includes:

an enable signal generating unit for generating a first enable signal which is initialized when the reset signal is activated and is activated when the reset signal is deactivated and generating a second enable signal which is activated after one period of the clock from an activation of the first enable signal;

a delayer for delaying the first enable signal to generate a delay signal; and

a sensing signal generating unit, which is initialized when the reset signal is activated, for generating the sensing signal in response to the delay signal and the second enable signal.

3. The delay circuit of claim 2 , wherein the enable signal generating unit generates the first enable signal which is initialized when the reset signal is activated and is activated when the reset signal is deactivated, and enables the second enable signal when the clock is transited to a high level twice after the first enable signal is activated.

4. The delay circuit of claim 3 , wherein the enable signal generating unit includes:

a first signal generating unit for inverting the reset signal to generate the first enable signal; and

a second signal generating unit for generating the second enable signal when the first enable signal is activated and the clock is transited to a high level twice.

5. The delay circuit of claim 4 , wherein the second signal generating unit includes first to third flip-flops which are in series connected to each other and transfers the first enable signal to output the second enable signal in response to the clock and wherein the first to third flip-flops are initialized in response to the reset signal.

6. The delay circuit of claim 5 , wherein the first flip-flop transfers the first enable signal to produce an output signal when the clock is in a high level, the second flip-flop transfers the output signal of the first flip-flop to produce an output signal when the clock is in a low level, and the third flip-flop transfers the output signal of the second flip-flop to produce the second enable signal when the clock is in a high level.

7. The delay circuit of claim 2 , wherein the sensing signal generating unit is initialized when the reset signal is activated and outputs the delay signal as the sensing signal when the second enable signal is activated.

8. The delay circuit of claim 7 , wherein the sensing signal generating unit includes a flip-flop which is initialized by the reset signal and outputs the delay signal as the sensing signal when the second enable signal is activated and, wherein the flip-flop is initialized in response to the reset signal.

9. The delay circuit of claim 1 , wherein the selective delay unit is configured to output the output signal by delaying the input signal for a delay time which is shorter than that at an activation of the sensing signal if the sensing signal is deactivated, and output the output signal by delaying the input signal for a delay time which is longer than that at an inactivation of the sensing signal if the sensing signal is activated.

10. The delay circuit of claim 9 , wherein the selective delay unit includes:

a first delayer for delaying and outputting the input signal;

a second delayer for delaying and outputting an output signal of the first delayer; and

a multiplexer for outputting the output signal of the first delayer or an output signal of the second delayer in response to the sensing signal.

11. A delay circuit of a semiconductor memory apparatus, comprising:

a clock period sensing unit for receiving an input clock and comparing a reference time with one period of a clock to generate a sensing signal; and

a selective delay unit for delaying an input signal for a delay time which is selected according to the sensing signal and outputting the input signal as an output signal,

wherein the clock period sensing unit is initialized when the reset signal is activated and compares a time when the clock is transited to a high level twice after the reset signal is deactivated with the reference time to generate the sensing signal.

12. The delay circuit of claim 11 , wherein the clock period sensing unit activates the sensing signal if one period of the clock is longer than the reference time and deactivates the sensing signal if one period of the clock is shorter than the reference time.

13. The delay circuit of claim 12 , wherein the clock period sensing unit includes:

an enable signal generating unit for generating a first enable signal which is activated when the reset signal is deactivated and outputting the first enable signal as a second enable signal when the clock is transited to a high level twice;

a delayer for delaying the first enable signal for the reference time to generate a delay signal; and

a sensing signal generating unit for outputting a level of the delay signal as the sensing signal when the second enable signal is activated.

14. The delay circuit of claim 13 , wherein the enable signal generating unit includes:

a first signal generating unit for generating the first enable signal which is activated when the reset signal is deactivated; and

a second signal generating unit for outputting the second enable signal by delaying the first enable signal from an inactivation of the reset signal until the clock is transited to a high level twice.

15. The delay circuit of claim 14 , wherein the second signal generating unit includes first to third flip-flops which are initialized when the reset signal is activated and operate in response to the clock and wherein the first to third flip-flops are in series connected.

16. The delay circuit of claim 15 , wherein the first flip-flop outputs the first enable signal as an output signal when the clock is in a high level, the second flip-flop outputs the output signal of the first flip-flop as an output signal when the clock is in a low level, and the third flip-flop outputs the output signal of the second flip-flop as the second enable signal when the clock is in a high level.

17. The delay circuit of claim 11 , wherein the selective delay unit outputs the output signal by delaying the input signal for a delay time which is shorter than that at an activation of the sensing signal if the sensing signal is deactivated and outputs the output signal by delaying the input signal for a delay time which is longer than an inactivation of the sensing signal if the sensing signal is activated.

18. The delay circuit of claim 17 , wherein the selective delay unit includes:

a first delayer for delaying and outputting the input signal;

a second delayer for delaying and outputting an output signal of the first delayer; and

a multiplexer for outputting the output signal of the first delayer or an output signal of the second delayer in response to the sensing signal.