IP Library Granted Patent US 7,996,804
Granted Patent B2
US 7,996,804 · App. 12/015,925 · Granted Aug 9, 2011

Signal delay skew reduction system

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Quick Facts
Patent No.
US 7,996,804
App. No.
12/015,925
Granted
Aug 9, 2011
Kind
B2
Abstract

A system for reducing the signal delay skew is disclosed, according to a variety of embodiments. One illustrative embodiment of the present disclosure is directed to a method. According to one illustrative embodiment, the method includes receiving an initial netlist comprising components and connection paths among the components. The method further includes identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist. The method also includes generating a skew-corrected netlist wherein the second connection path includes one or more added skew-influencing features corresponding to those of the first connection path. The method further includes outputting the skew-corrected netlist.

Claims (54)

1. A method comprising:

receiving an initial netlist comprising components and connection paths among the components;

identifying a skew group comprising a plurality of connection paths, including at least a first connection path and a second connection path, in the initial netlist;

performing with a computing device the following steps, prior to placement of the components:

identifying one or more skew-influencing features in a first connection path in the initial netlist that lack corresponding skew-influencing features in a second connection path in the initial netlist;

generating a skew-corrected netlist, prior to placement of the components, by adding one or more equivalent logic components of the same type to the second connection path corresponding to those of the first connection path, such that all the connection paths in the skew group have equivalent logic components;

identifying one or more driver pins or receiver pins in one or more of the connection paths in the skew group that lack equivalent driver pins or receiver pins in another one of the connection paths in the skew group, and adding the equivalent driver pins or receiver pins until all the connection paths in the skew group have equivalent driver pins and receiver pins and equivalent fanouts; and

outputting the skew-corrected netlist;

performing with the computing device the following steps after placement of the components in the skew-corrected netlist:

identifying one or more path fragments of one of the connection paths in the skew group that lack equivalent path fragments in another one of the connection paths in the skew group; and

re-routing the connection paths until all the connection paths in the skew group have equivalent path fragments.

2. The method of claim 1 , further comprising:

identifying one or more skew-influencing features in the second connection path in the initial netlist that lack corresponding skew-influencing features in the first connection path in the initial netlist; and

wherein generating the transformed netlist further comprises the first connection path comprising one or more added skew-influencing features corresponding to those of the second connection path.

3. The method of claim 1 , wherein at least one of the components is a buffer, an inverter, an AND gate, an OR gate, a NAND gate, a NOR gate, an XAND gate, an XOR gate, a splitter, a multiplexer, or a demultiplexer.

4. The method of claim 1 , wherein generating the skew-corrected netlist further comprises accompanying an addition or subtraction of a component of a certain type in one of the connection paths in the netlist, with a corresponding addition or subtraction of a component of the certain type to the other connection paths in the netlist.

5. The method of claim 1 , wherein re-routing comprises at least one of: providing the same number of path fragments in the first connection path as in the second connection path; providing the path fragments with equal lengths in the first connection path as in the second connection path; providing the path fragments with the same orientations in the first connection path as in the second connection path; and providing the path fragments in the same substrate layer in the first connection path as in the second connection path.

6. The method of claim 1 , wherein generating the skew-corrected netlist further comprises providing equivalent grounded shielding wires adjacent to at least a portion of all of the connection paths in the skew group.

7. The method of claim 6 , wherein providing grounded shielding comprises:

providing one or more shielding networks of horizontal and/or vertical ground wires connected to one or more ground pins;

providing conductive connections between one or more sets of the shielding wires, thereby grouping the one or more sets of the shielding wires into one or more shielding clusters; and

providing a conductive connection between each of the shielding wires and at least one of the ground pins, the shielding networks, or the shielding clusters.

8. The method of claim 7 , further comprising, for one or more of the shielding clusters, identifying a shortest available route along one of the shielding networks between the shielding cluster and either another shielding cluster or a ground pin, and providing a conductive connection for the shielding cluster along that shortest available route.

9. The method of claim 7 , wherein the conductive connections comprise at least one of: a horizontal conductive segment within a substrate, and a vertical via between two or more substrates.

10. The method of claim 1 , wherein the connection paths are comprised in a common signal propagation tree.

11. The method of claim 10 , wherein the signal propagation tree consists of either: a single data rate source synchronous interface; a double data rate source synchronous interface; or a heterogeneous logic block global clock tree.

12. The method of claim 1 , further comprising manufacturing an integrated circuit using a design derived at least in part from the skew-corrected netlist.

13. A non-transitory medium comprising executable instructions capable of being read and executed by a computing system and thereby configuring the computing system to receive a logic design and to provide a corresponding physical design embodying the logic design, wherein the computing system executing the instructions comprises:

a feature identifying a skew group comprising a plurality of connection paths;

a path equalization feature, configured to compare components associated with different connection paths within a signal propagation tree comprised in the logic design within the skew group, and to add components to one or more of the connection paths in the skew group to correspond to components of a same type found on one or more of the other connection paths in the skew group; identify any of the connection paths within the skew group having different numbers of components of the same type, compared with another connection path within the skew group, and add components to the connection paths until all the connection paths within the skew group have the same number of components of the same types; and

identify any of the connection paths within the skew group without equivalent driver pins or receiver pins to those in another connection path within the same skew group; and add driver pins and receiver pins to the connection paths in the skew group until all the connection paths within the skew group have equivalent sets of driver pins and receiver pins;

an enhanced timing closure feature, configured to duplicate component changes made to one of the connection paths in the skew group on other connection paths in the skew group;

an equivalent routing feature, configured to re-route two or more of the connection paths within the skew group to have equivalent path fragments; and

a grounded shielding feature, configured to provide grounded shielding wires adjacent to at least a portion of one or more of the connection paths in the skew group.

14. A method comprising:

receiving an initial netlist comprising components among the components along one or more signal propagation trees;

identifying a skew group comprising a plurality of the connection paths;

performing with a computing device the following steps, prior to placement of the components:

identifying one or more logic components in one or more of the connection paths in the skew group that lack equivalent logic components of a same type in another one of the connection paths in the skew group, and adding the equivalent logic components until all the connection paths in the skew group have equivalent logic components; and

identifying one or more driver pins or receiver pins in one or more of the connection paths in the skew group that lack equivalent driver pins or receiver pins in another one of the connection paths in the skew group, and adding the equivalent driver pins or receiver pins until all the connection paths in the skew group have equivalent driver pins and receiver pins such that each driver pin in one of the connection paths in the skew group has an equivalent fanout as corresponding driver pins corresponding connection paths in the skew group;

performing with the computing device the following steps after placement of the components:

identifying one or more path fragments of one of the connection paths in the skew group that lack equivalent path fragments in another one of the connection paths in the skew group, and re-routing the connection paths until all the connection paths in the skew group have equivalent path fragments; and

providing equivalent grounded shielding wires adjacent to the connection paths in the skew group; and

outputting a skew-corrected netlist comprising the connection paths in the skew group having equivalent logic components, equivalent driver pins and receiver pins, equivalent path fragments, and equivalent grounded shielding.

15. A non-transitory medium comprising executable instructions capable of being read and executed by a computing system and thereby configuring the computing system to receive a logic design and to provide a corresponding physical design embodying the logic design, wherein the computing system executing the instructions performs a method comprising:

receiving an initial netlist comprising components and connection paths among the components;

identifying a skew group comprising a plurality of connection paths in the initial netlist;

performing with a computing device the following steps, prior to placement of the components:

generating a skew-corrected netlist, prior to placement of the components, by adding one or more equivalent logic components of a same type to one or more connection paths in the skew group corresponding to those of another of the connection paths in the skew group, such that all the connection paths in the skew group have equivalent logic components of the same type;

identifying one or more driver pins or receiver pins in one or more of the connection paths in the skew group that lack equivalent driver pins or receiver pins in another one of the connection paths in the skew group, and adding the equivalent driver pins or receiver pins until all the connection paths in the skew group have equivalent driver pins and receiver pins and equivalent fanouts; and

outputting the skew-corrected netlist;

performing with the computing device the following steps after placement of the components in the skew-corrected netlist:

identifying one or more path fragments of one of the connection paths in the skew group that lack equivalent path fragments in another one of the connection paths in the skew group; and

re-routing the connection paths until all the connection paths in the skew group have equivalent path fragments.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
CHANGE OF NAME Recorded Jul 12, 2012
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 028538/0734 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2012
From: NIKITIN, ANDREY; SCEPANOVIC, RANKO; KUCHERENKO, IGOR; LAU, WILLIAM; KONG, CHENG-GENG; SETO, HUI-YIN; ZOLOTYKH, ANDREJ; PAVISIC, IVAN; BHUTANI, SANDEEP; LU, AIGUO; LYALIN, ILYA
To: LSI LOGIC CORPORATION
Reel/Frame 028516/0201 →