Granted Patent B2

US 7,514,318 · App. 12/016,904 · Granted Apr 7, 2009

Assignee: Micrel, Inc.

Abstract

Claims (21)

1. A method for fabricating a non-volatile memory cell, the method comprising:

providing a substrate of a first conductivity type;

forming a first dopant region of a second conductivity type in the substrate;

forming a second dopant region of the first conductivity type in the first dopant region;

growing a first isolation region over a first portion of the substrate, the first dopant region, and the second dopant region, the first isolation region being in contact with the substrate, the first dopant region, and the second dopant region;

growing a second isolation region over a second portion of the substrate, the first dopant region, and the second dopant region, the second isolation region being in contact with the substrate, the first dopant region, and the second dopant region;

defining a contact region of the first conductivity type in the second dopant region, the contact region extending between the first isolation region and the second isolation region such that the first isolation region and the second isolation region are both in contact with the contact region, the contact region being more heavily doped than the second dopant region;

depositing a gate oxide layer to form a first gate dielectric atop the first isolation region and a portion of the contact region; and

overlaying a gate conductive layer on top of the gate oxide layer to form a first gate conductor atop the first gate dielectric.

2. The method of claim 1 , further comprising:

forming a third dopant region of the first conductivity type in the substrate, wherein deposition of the gate oxide layer further forms a second gate dielectric atop the third dopant region and overlay of the gate conductive layer further forms a second gate conductor atop the second gate dielectric, the second gate conductor being coupled to the first gate conductor;

defining a source region of the second conductivity type in the third dopant region, the source region being in contact with the second gate dielectric; and

defining a drain region of the second conductivity type in the third dopant region, the drain region being in contact with the second gate dielectric.

3. The method of claim 2 , wherein the first gate conductor and the second gate conductor comprise part of a single conducting trace.

4. The method of claim 2 , wherein the source region and the drain region are symmetrical.

5. The method of claim 2 , wherein the source region and the drain region comprise only arsenic.

6. The method of claim 2 , further comprising:

creating a plurality of spacers, wherein a first of the plurality of spacers is only in contact with the second gate dielectric, the second gate conductor, and the source region, and a second of the plurality of spacers is only in contact with the second gate dielectric, the second gate conductor, and the drain region.

7. The method of claim 1 , wherein the first conductivity type is P-type and the second conductivity type is N-type.

8. The method of claim 1 , wherein the second dopant region, the contact region, the first gate dielectric, and the first gate conductor form a coupling capacitor.

9. The method of claim 1 , wherein the non-volatile memory cell does not include any lightly-doped drain regions.

Assignments (10)

Continuity (2)