Alternate sensing techniques for non-volatile memories
View Patent ↗The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
1. A method of concurrently determining the state of a plurality of multi-state memory cells from a memory array, wherein said plurality of memory cells are connected along a common word line, have sources connected to a common source line, and are formed along distinct bit lines, the method comprising:
discharging the memory cells to ground through the corresponding bit lines;
subsequently applying a first voltage level to the common source line;
subsequently applying a second voltage level to the word line;
in response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a first subset of said multi-states;
subsequently applying a third voltage level to the word line, wherein the third voltage level differs from the second voltage level; and
in response to applying the third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.
2. The method of claim 1 , wherein determining whether the data content of each of the memory cells corresponds to one of a first or second subset of said multi-states includes:
allowing a voltage to develop upon each of the corresponding bit lines; and
comparing the voltages developed along the bit lines to a plurality of reference values in order to determine the data content of the memory cells.
3. The method of claim 1 , wherein the first and second subsets of said multi-states are non-overlapping.
4. The method of claim 1 , wherein the combination of the first and second subsets of said multi-states contain less than all of said multi-states.
5. The method of claim 1 , wherein said array has a NAND architecture.
6. The method of claim 1 wherein said array has an all bit line architecture.
7. The method of claim 1 , wherein determining whether the data content of each of the memory cells corresponds to one of a first subset and determining whether the data content of each of the memory cells corresponds to one of a second subset are performed during the verification phase of a write operation.
8. The method of claim 1 , wherein determining whether the data content of each of the memory cells corresponds to one of a first subset and determining whether the data content of each of the memory cells corresponds to one of a second subset are performed during a read operation.
9. A method of writing multi-state data concurrently to a plurality of multi-state memory cells from a memory array, wherein said plurality of memory cells are connected along a common word line, have sources connected to a common source line, and are formed along distinct bit lines, the method comprising:
applying a common programming pulse to the word line while controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells; and
subsequently performing a verify operation, comprising:
discharging the memory cells to ground through the corresponding bit lines;
subsequently applying a first voltage level to the common source line;
subsequently applying a second voltage level to the word line;
in response to applying the second voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a first subset of said multi-states;
subsequently applying a third voltage level to the word line, wherein the third voltage level differs from the second voltage level; and
in response to applying the third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of a second subset of said multi-states, wherein the first and second subsets of said multi-states are distinct and each contain a plurality of states.
10. The method of claim 9 , wherein determining whether the data content of each of the memory cells corresponds to one of a first or second subset of said multi-states includes:
allowing a voltage to develop upon each of the corresponding bit lines; and
comparing the voltages developed along the bit lines to a plurality of reference values in order to determine the data content of the memory cells.
11. The method of claim 9 , wherein said controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells includes setting a voltage level on said bit lines on a bit line by bit line basis based on said corresponding target state of each of said memory cells.
12. The method of claim 9 , wherein said controlling the amount of charge injected into each of said memory cell on a bit line by bit line basis based on the corresponding target state of each of said memory cells includes setting a current limit on said bit lines on a bit line by bit line basis based on said corresponding target state of each of said memory cells.