SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers, a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed within the stack structure, and a charge storage layer that is provided between the gate electrode and the channel layer.
1 . A semiconductor device comprising:
a stack structure in which multiple channel layers are stacked on a substrate so as to be sandwiched between bit line layers;
a gate electrode that is provided to a side of a lateral surface exposed in a groove portion formed within the stack structure; and
a charge storage layer provided between the gate electrode and the channel layer.
2 . The semiconductor device according to claim 1 , wherein the groove portion is formed to reach a lower surface of a lowermost channel layer of the stack structure.
3 . The semiconductor device according to claim 1 , further comprising multiple word lines provided over the stack structure, wherein each of the multiple word lines is connected to multiple gate electrodes disposed in a width direction of the groove portion.
4 . The semiconductor device according to claim 3 , wherein the multiple word lines are electrically separated from each other.
5 . The semiconductor device according to claim 1 , wherein the multiple channel layers comprise polysilicon.
6 . The semiconductor device according to claim 1 , wherein one of the bit line layers between adjacent channel layers among the multiple channel layers is shared by the adjacent channel layers.
7 . The semiconductor device according to claim 1 , further comprising an insulating layer provided in one of the bit line layers provided between adjacent channel layers among the multiple channel layers so that the one of the bit line layers is divided into portions respectively associated with the adjacent channel layers.
8 . The semiconductor device according to claim 1 , wherein the charge storage layer comprises a silicon nitride film sandwiched between silicon oxide films.
9 . A semiconductor device comprising:
multiple semiconductor layers which have source drain regions and channel regions disposed alternately in a lateral direction and stacked in a longitudinal direction so that the source drain regions and the channel regions are superposed longitudinally and are insulated from each other;
gate electrodes that are provided to sides of the channel regions at a lateral surface of a groove portion formed in the multiple semiconductor layers and extending in the lateral direction;
a charge storage layer that is provided between the channel region and the gate electrode; and
an insulating layer that is provided to the side of the source drain region at the lateral surface of the interior of the groove portion.
10 . The semiconductor device according to claim 9 , wherein the source drain region and the channel region disposed alternately in the lateral direction constitute a NAND cell.
11 . The semiconductor device according to claim 9 , wherein the semiconductor layer contains polysilicon.
12 . A semiconductor device comprising:
a first bit line layer that is provided over a substrate;
a channel layer containing polysilicon that is provided over the first bit line layer;
a second bit line layer that is provided over the channel layer;
a gate electrode that is provided to the side of the lateral surface of an interior of a groove portion formed in the channel layer; and
a charge storage layer that is provided between the gate electrode and the channel layer.
13 . A method for manufacturing a semiconductor device, comprising:
stacking multiple channel layers, sandwiched between bit line layers above and below, over a substrate;
forming a groove portion in the multiple channel layers so as to reach the lower surface of the lowermost channel layer;
forming a charge storage layer to the side of the lateral surface of the groove portion; and
forming a gate electrode inside the groove portion.
14 . The method for manufacturing a semiconductor device according to claim 13 , wherein forming the gate electrode includes forming over the stack structure multiple word lines that are disposed in the width direction of the groove portion and connected to the gate electrode.
15 . The method for manufacturing a semiconductor device according to claim 13 , wherein the stacking of the multiple channel layers is implemented by using a silicon oxide layer to stick multiple silicon substrates together.
16 . A method for manufacturing a semiconductor device, comprising:
stacking multiple semiconductor layers so as to be insulated from one another;
forming a source drain region and a channel region alternately in the lateral direction inside the semiconductor layer;
forming a groove portion in the multiple semiconductor layers so as to reach as far as the lower surface of the lowermost semiconductor layer;
forming a charge storage layer to the side of the lateral surface of the interior of the groove portion; and
forming a gate electrode inside the groove portion.
17 . The method for manufacturing a semiconductor device according to claim 16 , wherein forming the gate electrode includes forming, over the stack structure and so as to be connected, multiple gate electrodes that are disposed in the width direction of the groove portion.