Decoding system capable of charging protection for flash memory devices
The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further includes a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.
1. A memory array comprising:
a first insulating/dielectric layer formed on a semiconducting body;
a charge trapping dielectric layer formed over the first insulating/dielectric layer;
a second insulating/dielectric layer formed over the charge trapping dielectric layer;
at least one bit line formed in the semiconducting body that respectively operates as an acting source and acting drain;
a discharging circuit, wherein the discharging circuit is electrically connected to a first discharge terminal;
a first word line formed over the second insulating/dielectric layer and orthogonal to the at least one bit line;
a second word line formed over the second insulating/dielectric layer and orthogonal to the at least one bit line and parallel to the first word line, wherein the second word line is directly coupled to the discharging circuit exclusively by a contact level and a first metal level; and
a shorting path electrically connecting the first word line to the second word line, wherein the shorting path comprises a resistance higher than the first word line or the second word line.
2. The memory array of claim 1 , wherein the discharging circuit comprises a diode junction.
3. The memory array of claim 2 , wherein the diode junction is part of a periphery decoder circuit.
4. The memory array of claim 3 , further comprising a semiconductor diode, wherein the semiconductor diode is directly coupled to a second discharge terminal and the shorting path exclusively by the contact level and the first metal level.
5. The memory array of claim 4 , wherein the semiconductor diode comprises an n-well implant in a p-well.
6. The memory array of claim 5 , wherein the p-well comprises the same p-well of the periphery decoder circuit.
7. The memory array of claim 1 , wherein the shorting path comprises an undoped gate electrode material.
8. The memory array of claim 7 , wherein the resistance of the undoped gate electrode material is on the order of 10's of mega ohms.
9. The memory array of claim 1 , further comprising an additional word line formed over the second insulating/dielectric layer orthogonal to the at least one bit line and parallel to the first and second word lines, wherein the additional word line is electrically connected to the shorting path.
10. The memory array of claim 9 , further comprising an additional discharging circuit electrically connected to the additional word line and an additional discharge terminal.