Data processor and memory read active control method
Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.
1. A data processor, comprising;
a cache unit having a plurality of cache memories;
a branch prediction unit, when an instruction is a branch instruction, configured to perform a conditional branch prediction indicating whether a conditional branch of the branch instruction is taken or not taken and a cache WAY prediction indicating in which cache memory, from among the plurality of cache memories, data of the branch instruction is stored and to output a branch prediction data which is based on the conditional branch prediction and the cache WAY prediction; and
a control unit configured to control an activation of each of the plurality of cache memories,
wherein the branch prediction data has a plurality of states which transits between each other in response to a result of the conditional branch prediction and the cache WAY prediction,
wherein the control unit is configured to control the activation of each of the plurality of cache memories based on a current state of the branch prediction data among the plurality of states.
2. The data processor according to claim 1 , wherein
the control unit activates at least one of the plurality of cache memories corresponding to the branch prediction data when the branch prediction data indicates that a last one of the conditional branch is taken, and a last one of the cache WAY prediction is hit.
3. The data processor according to claim 2 , wherein
the control unit activates all of the plurality of cache memories when the branch prediction data indicates that a last one of the conditional branch is taken and a last one of the cache WAY prediction is miss.
4. An activation control method of a plurality of cache memories in cache unit, comprising;
when an instruction is a branch instruction, performing a conditional branch prediction indicating whether a conditional branch of the branch instruction is taken or not taken and a cache WAY prediction indicating in which cache memory, from among the plurality of cache memories, data of the branch instruction is stored;
outputting a branch prediction data which is based on the conditional branch prediction and the cache WAY prediction; and
controlling an activation of each of the plurality of cache memories,
wherein the branch prediction data has a plurality of states which transits between each other in response to a result of the conditional branch prediction and the cache WAY prediction,
wherein the activation of each of the plurality of cache memories is controlled based on a current state of the branch prediction data among the plurality of states.
5. The activation control method of claim 4 , wherein
the controlling includes activating at least one of the plurality of cache memories corresponding to the branch prediction data when the branch prediction data indicates that a last one of the conditional branch is taken and a last one of the cache WAY prediction is hit.
6. The activation control method of claim 5 , wherein
the controlling includes activating all of the plurality of cache memories when the branch prediction data indicates that a last one of the conditional branch is taken and a last one of the cache WAY prediction is miss.