Warpage resistant semiconductor package and method for manufacturing the same
View Patent ↗A semiconductor package and a method for manufacturing the same is provided for minimizing or preventing warpage and twisting of semiconductor chip bodies as a result of thinning them during grinding. The semiconductor package includes a semiconductor chip body and a substrate. The semiconductor chip body has a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface. The substrate has a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.
1. A semiconductor package comprising:
a semiconductor chip having a semiconductor chip body having a first surface, a second surface facing away from the first surface, through-electrodes which pass through the semiconductor chip body and which project from the second surface, and a warpage prevention part which projects in the shape of a fence along an edge of the second surface; and
a substrate having a substrate body and connection pads which are formed on an upper surface of the substrate body, facing the second surface, and which are connected with the projecting through-electrodes.
2. The semiconductor package according to claim 1 , wherein the semiconductor chip body is located in a chip region, and the warpage prevention part is located along scribe line regions which are defined around the chip region.
3. The semiconductor package according to claim 1 , wherein a length of the through-electrodes, which project from the second surface, is substantially the same as a height of the warpage prevention part.
4. The semiconductor package according to claim 1 , wherein the warpage prevention part is intermittently formed on the second surface.
5. The semiconductor package according to claim 1 , wherein the through-electrodes projecting from the second surface include solder members.
6. The semiconductor package according to claim 1 , wherein at least two semiconductor chips are located on the substrate.
7. The semiconductor package according to claim 1 , further comprising:
bonding pads located on the first surface with the through-electrodes respectively passing through the bonding pads.