Serial-to-parallel converter circuit and liquid crystal display driving circuit
View Patent ↗A serial-to-parallel converter circuit comprising: an m-bit serial data holding unit to be input with serial data whose input bit number is set to m or n (<m) bits within a transfer period and a serial clock synchronized therewith, and to shift and hold the serial data by one bit based on the serial clock; an input mode identifying unit to identify whether the input bit number is m or n bits, based on a count value obtained by counting the number of generation of the serial clock during the transfer period; and a parallel data generating unit to output the held m-bit data as first parallel data when the input bit number is identified as m bits, and to output m-bit data obtained by adding predetermined (m−n)-bit data to the held n-bit data as second parallel data when the input bit number is identified as n bits.
1. A serial-to-parallel converter circuit for converting serial data into parallel data to be output, comprising:
an m-bit serial data holding unit configured to be input with serial data and a serial clock synchronized with the serial data, an input bit number of the serial data being set to be m bits or n bits smaller than the m bits within a transfer period from transfer start to transfer completion, and configured to shift and hold the serial data by one bit based on the serial clock;
an input mode identifying unit configured to identify whether the input bit number is m bits or n bits, based on an count value obtained by counting the number of generation of the serial clock during the transfer period; and
a parallel data generating unit configured to output m-bit data held in the m-bit serial data holding unit as first parallel data when the input mode identifying unit identifies the input bit number to be m bits, and configured to output m-bit data obtained by adding predetermined (m−n)-bit data to n-bit data held in the m-bit serial data holding unit as second parallel data when the input mode identifying unit identifies the input bit number to be n bits.
2. The serial-to-parallel converter circuit according to claim 1 , wherein
the parallel data generating unit
performs a conversion in arrangement for m-bit data obtained by adding predetermined (m−n)-bit data to n-bit data held in the serial data holding unit, corresponding to a circuit at a subsequent stage, and
outputs the m-bit data converted in arrangement as the second parallel data,
when the input mode identifying unit identifies the input bit number to be n bits.
3. The serial-to-parallel converter circuit according to claim 1 , further comprising:
a transfer completion identifying unit configured to identify the transfer completion; and
a parallel data holding unit configured to hold and output the first parallel data or the second parallel data, based on: an output of the input mode identifying unit when identifying the input bit number to be m bits or n bits; and an output of the transfer completion identifying unit when identifying the transfer completion.
4. The serial-to-parallel converter circuit according to claim 1 , wherein:
a three-wire serial interface of the serial data, the serial clock, and a chip enable is used;
transfer starts when the chip enable changes from one level to the other level;
transfer completes when the chip enable changes from the other level to the one level; and
the serial data is input in synchronization with the serial clock, the input bit number of the serial data being set to be m bits or n bits within the transfer period in which the chip enable changes to the other level.
5. The serial-to-parallel converter circuit according to claim 1 , wherein:
a four-wire serial interface of serial input data and serial output data as the serial data, the serial clock, and a chip enable is used;
transfer starts when the chip enable changes from one level to the other level;
transfer completes when the chip enable changes from the other level to the one level; and
the serial data is input in synchronization with the serial clock, the input bit number of the serial data being set to be m bits or n bits within the transfer period in which the chip enable changes to the other level.
6. The serial-to-parallel converter circuit according to claim 4 , wherein:
the chip enable is set to the one level and an address code is transferred as the serial data in synchronization with the serial clock, and thereafter the chip enable is changed from the one level to the other level and the serial data is transferred, the input bit number of the serial data being set to be m bits or n bits; and
a serial interface circuit is provided at a previous stage, the serial interface circuit being configured to input to the serial-to-parallel converter circuit the serial clock and the serial data transferred when the chip enable is at the other level, when the address code transferred when the chip enable is at the one level coincides with an address code given to the serial-to-parallel converter circuit.
7. The serial-to-parallel converter circuit according to claim 1 , wherein:
a two-wire serial interface of the serial data and the serial clock is used;
a start bit and a stop bit are added before and after the serial data whose input bit number is set to be m bits or n bits;
the transfer start is performed by the start bit; and
the transfer completion is performed by the stop bit.
8. A liquid crystal display driving circuit for driving a liquid display panel, comprising:
an m-bit serial data holding unit configured to be input with serial data as display data of the liquid crystal display panel and a serial clock synchronized with the serial data, an input bit number of the serial data being set to be m bits or n bits smaller than the m bits within a transfer period from transfer start to transfer completion, and configured to shift and hold the serial data by one bit based on the serial clock;
an input mode identifying unit configured to identify whether the input bit number is m bits or n bits, based on an count value obtained by counting the number of generation of the serial clock during the transfer period; and
a parallel data generating unit configured to output m-bit data held in the m-bit serial data holding unit as first parallel data when the input mode identifying unit identifies the input bit number to be m bits, and configured to output m-bit data obtained by adding predetermined (m−n)-bit data to n-bit data held in the m-bit serial data holding unit as second parallel data when the input mode identifying unit identifies the number of input bits to be n bits.