Insulated gate semiconductor device
View Patent ↗An isolation region is provided around a sense part. The isolation region is provided to have a depth that suppresses spread of a region with an uneven current distribution, which occurs at a peripheral edge of the sense part. Thus, in the sense part, an influence of the region with the uneven current distribution can be suppressed. Since the current distribution can be set more even throughout the sense part, the on-resistance in the sense part can be set closer to its designed value. Thus, a current ratio corresponding to a cell ratio can be obtained as designed. Consequently, current detection accuracy is improved.
1. An insulated gate semiconductor device comprising:
a semiconductor substrate of a first general conductivity type;
a semiconductor layer of the first general conductivity type disposed on the semiconductor substrate;
a first channel region of a second general conductivity type formed in the semiconductor layer;
a second channel region of the second general conductivity type formed in the semiconductor layer;
a first operation part comprising the first channel region and a plurality of first transistors each comprising a portion of the first channel region, the first transistors comprising corresponding trenches formed in the first channel region;
a second operation part comprising the second channel region and a plurality of second transistors each comprising a portion of the second channel region, the second operation part being smaller than the first operation part, the second transistors comprising corresponding trenches formed in the second channel region; and
an isolation region surrounding the second operation part and penetrating into the semiconductor layer and physically in contact with neither the first channel region nor the second channel region,
wherein the isolation region penetrates deeper into the semiconductor layer than the trenches of the first and second transistors.
2. The insulated gate semiconductor device of claim 1 , wherein the isolation region is deep enough to suppress a horizontal spread of a current flowing into the semiconductor layer from the second channel region.
3. The insulated gate semiconductor device of claim 1 , wherein the isolation region is deeper than the second channel region.
4. The insulated gate semiconductor device of claim 1 , wherein the isolation region comprises an insulating layer.
5. The insulated gate semiconductor device of claim 1 , wherein the isolation region comprises a high concentration impurity region of the second general conductivity type.
6. The insulated gate semiconductor device of claim 1 , wherein the isolation region comprises a through-hole penetrating the semiconductor layer and the semiconductor substrate and an insulating film formed on a side wall of the through-hole.
7. The insulated gate semiconductor device of claim 1 , wherein the first and second transistors comprise gate electrodes connected to a common gate electrode terminal.
8. The insulated gate semiconductor device of claim 1 , wherein the second transistors are configured to detect a current in the first transistors.
9. The insulated gate semiconductor device of claim 1 , wherein the isolation region is deep enough to be physically in contact with the semiconductor substrate.