Semiconductor device and manufacturing method thereof
View Patent ↗In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3 . A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8 . Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9 , the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3 . Thus, a resistance value on the pad electrode 3 is reduced.
1. A semiconductor device comprising: a pad electrode formed on a semiconductor substrate; an insulating layer formed on the semiconductor substrate so as to cover the pad electrode and having a plurality of openings over the pad electrode; a metal layer formed on the insulating layer so as to be connected to the pad electrode through the openings, the metal layer not filling the openings fully so as to form a concave portion at each of the openings; a plating metal layer formed on the metal layer so that a portion of the plating metal layer disposed in each of the concave portions becomes thinner than other portions of the plating metal layer; and an electrode formed on the plating metal layer so that part of the electrode and part of the metal layer are alloyed through the thinner portion of the plating metal layer, wherein the plating metal layer comprises chromium, the plating metal layer has an area without crystal grains in the thinner portion, and a chromium alloy is formed in the area without crystal grains.
2. The semiconductor device of claim 1 , wherein the thinner portion is located at a bottom corner of a corresponding concave portion.
3. The semiconductor device of claim 2 , wherein each of the openings is formed so that an angle between a sidewall of the opening and the pad electrode covered by the insulating layer is 70° to 90°.
4. The semiconductor device of claim 1 , wherein the metal layer comprises aluminum or an aluminum alloy, and the electrode comprises a copper layer and a bump electrode formed on the copper layer.
5. The semiconductor device of claim 1 , further comprising a spin-coated resin film formed on the metal layer and having an opening in which the concave portions are located.
6. The semiconductor device of claim 5 , wherein the spin-coated resin film comprises a polybenzoxazole or a polyimide resin.
7. A semiconductor device comprising: a pad electrode formed on a semiconductor substrate;
an insulating layer formed on the semiconductor substrate so as to cover the pad electrode and having a plurality of openings over the pad electrode;
a plating metal layer formed on the insulating layer so as to be connected to the pad electrode through the openings, a portion of the plating metal layer disposed in each of the openings being thinner than other portions of the plating metal layer; and
an electrode formed on the plating metal layer so that part of the electrode and part of the pad electrode are alloyed through the thinner portion of the plating metal layer, wherein the plating metal layer comprises chromium, the plating metal layer has an area without crystal grains in the thinner portion, and a chromium alloy is formed in the area without crystal grains.
8. The semiconductor device of claim 7 , wherein the thinner portion is located at a bottom corner of a corresponding opening.
9. The semiconductor device of claim 8 , wherein each of the openings is formed so that an angle between a sidewall of the opening and the pad electrode covered by the insulating layer is 70° to 90°.
10. The semiconductor device of claim 7 , wherein the pad electrode comprises aluminum or an aluminum alloy, and the electrode comprises a copper layer and a bump electrode formed on the copper layer.
11. The semiconductor device of claim 7 , further comprising a spin-coated resin film formed on the metal layer and having an opening in which the openings of the insulating layer are located.
12. The semiconductor device of claim 11 , wherein the spin-coated resin film comprises a polybenzoxazole or a polyimide resin.