Dual bit flash memory devices and methods for fabricating the same
View Patent ↗Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.
1. A nonvolatile semiconductor memory device comprising:
a semiconductor substrate;
two spaced-apart charge storage nodes disposed on the substrate;
two spaced-apart bitline regions disposed within the substrate, wherein each of the two spaced-apart bitline regions is in electrical contact with one of the two spaced-apart charge storage nodes;
a gate insulator disposed on the substrate between the two spaced-apart charge storage nodes;
a gate spacer disposed on the gate insulator and between the two spaced-apart charge storage nodes; and
a word line in physical contact with the gate spacer and the two spaced-apart charge storage nodes.
2. The nonvolatile semiconductor memory device of claim 1 , wherein the two spaced-apart charge storage nodes have substantially vertical sidewalls.
3. The nonvolatile semiconductor memory device of claim 1 , wherein the two spaced-apart charge storage nodes each comprises a charge trapping layer and a gate structure overlying the charge trapping layer.
4. The nonvolatile semiconductor memory device of claim 3 , wherein the charge trapping layer is comprised of silicon-rich silicon nitride, silicon nitride, polycrystalline silicon, or a combination thereof.
5. The nonvolatile semiconductor memory device of claim 3 , wherein the gate structure is comprised of polycrystalline silicon.
6. The nonvolatile semiconductor memory device of claim 1 , wherein the gate spacer is comprised of polycrystalline silicon.