Multilevel magnetic storage device
The present invention includes a memory configured to store data having a pinned layer and a plurality of stacked memory locations. Each memory location includes a nonmagnetic layer and a switchable magnetic layer. The plurality of stacked memory locations are capable of storing a plurality of data bits.
1. An apparatus comprising:
a single pinned layer with a fixed magnetic orientation; and
a plurality of stacked memory locations coupled to the single pinned layer each including a switchable magnetic layer having a first and a second resistance state, each said state established in relation to a magnetic orientation of the switchable magnetic layer relative to the fixed magnetic orientation of the single pinned layer.
2. The apparatus of claim 1 wherein each of the plurality of memory locations include a non-magnetic layer.
3. The apparatus of claim 2 wherein the nonmagnetic layer comprises a layer selected from the group of layers consisting of an insulator layer, a semiconductor layer, and a metal layer.
4. The apparatus of claim 1 wherein each of the plurality of memory locations further comprises a tunneling layer, the respective switchable magnetic layers and the tunneling layers of said plurality of memory locations alternately arranged in a semiconductor memory cell stack on the single pinned layer.
5. The apparatus of claim 1 wherein the switchable magnetic layer is selected from the group of layers consisting of a magnetic layer proximate to an antiferromagnetic layer, a high anisotropy layer, and a synthetic antiferromagnetic layer.
6. The apparatus of claim 3 wherein the switchable magnetic layer comprises a magnetic layer adjacent a high anisotropy layer.
7. The apparatus of claim 1 including a controller configured to control a current source configured to provide a recording current to the memory locations and thereby switch at least one of the plurality of switchable magnetic layers from the first resistance state to the second resistance state and thereby store a digital value.
8. The apparatus of claim 1 in which the stack has a first overall width and the pinning layer has a second greater width.
9. The apparatus of claim 1 wherein the pinned layer is selected from the group of layers consisting of a magnetic layer adjacent an antiferromagnetic layer, a high anisotropy layer, and a synthetic antiferromagnetic layer.
10. The apparatus of claim 1 further comprising a sensor configured to sense a resistance of at least one of the plurality of memory locations and thereby retrieve a stored digital value.
11. A method of storing data, comprising:
providing a memory cell with a single pinned layer having a fixed magnetic orientation and a plurality of stacked memory locations coupled to the single pinned layer, each memory location including a switchable magnetic layer having a first and a second resistance state, each said state established in relation to a magnetic orientation of the switchable magnetic layer relative to the fixed magnetic orientation of the single pinned layer;
applying a first current through the plurality of memory locations to cause at least one of the plurality of memory locations to obtain a first electrical resistance level and thereby store a digital value; and
sensing a resistance of at least one of the plurality of memory locations and thereby retrieving the stored digital value.
12. The method of claim 11 wherein sensing a resistance includes applying a second current level and wherein the first and second current levels are different.
13. The method of claim 11 including applying a second current level to the plurality of memory locations and causing the plurality of memory locations to attain a second electrical resistance value.
14. The method of claim 11 where first the resistance value is measured and this value is used in determining a series of current value needed to reach a desired final state.
15. The method of claim 11 including applying a resetting current to set the switchable layers to a known state prior to applying current to write a data bit.
16. The method of claim 11 wherein a block of data bits is written to a plurality of stacked memory locations all at once.
17. The method of claim 11 wherein each of the plurality of memory locations further comprises a layer selected from the group of layers consisting of an insulator layer, a semiconductor layer, and a metal layer.
18. The method of claim 11 wherein the switchable magnetic layer is selected from the group of layers consisting of a magnetic layer proximate to an antiferromagnetic layer, and a high anisotropy layer, a synthetic antiferromagnetic layer.
19. The method of claim 13 further comprising providing the first and second currents from a current source.
20. The method of claim 11 including switching each of the plurality of stacked memory locations between two resistive states.
21. A method of storing data, comprising:
providing a memory cell with a single pinned layer having a fixed magnetic orientation and a plurality of stacked memory locations coupled to the single pinned layer, each memory location including a switchable magnetic layer having a first and a second resistance state, each said state established in relation to a magnetic orientation of the switchable magnetic layer relative to the fixed magnetic orientation of the single pinned layer;
writing data to a read/write channel in the plurality of stacked memory locations; and
causing the data written to the read/write channel to propagate to an adjacent memory location in the plurality of stacked memory locations.
22. The method of claim 21 including providing a transducer to read and write data to the read/write channel.
23. The method of claim 21 including sensing resistance of the read/write channel to read back data.
24. The method of claim 21 including providing a current source coupled to opposite ends of the stacked magnetic memory locations to propagate the data to an adjacent location.
25. The method of claim 21 wherein at least one location of the plurality of stacked magnetic memory locations has at least two stable magnetic states.
26. The method of claim 21 including propagating the written data to a buffer location.
27. A semiconductor memory cell, having a plurality of switchable magnetic layers with selectively variable magnetic orientations each magnetically coupled to a single pinned layer having a fixed magnetic orientation, wherein the respective switchable magnetic layers are switched between a parallel configuration and an antiparallel configuration relative to the fixed magnetic orientation of the pinned layer to set an overall electrical resistance of the memory cell.
28. The memory cell of claim 27 , characterized as a stack of the switchable magnetic layers with tunneling barriers interposed therebetween, wherein a spin torque is induced in a current passed through the single pinned layer and passed through each of the switchable magnetic layers to change the respective magnetic orientation of each said magnetic layer.
29. The memory cell of claim 27 , wherein the switchable magnetic layers have a first overall diameter in a direction perpendicular to a direction of current flow through the memory cell, and the pinned layer has a second overall diameter in a direction perpendicular to said direction of current flow greater than the first overall diameter.