Semiconductor device
View Patent ↗Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.
1. A discrete semiconductor element comprising an input portion and an output portion, comprising:
a semiconductor substrate of a first general conductivity type;
a semiconductor layer of the first general conductivity type disposed on the semiconductor substrate;
a device region formed in the semiconductor layer and configured to operate as an active region of the discrete semiconductor element;
an impurity region of the first general conductivity type formed on an edge portion of the semiconductor layer so as to surround the device region and to penetrate the semiconductor layer to reach the semiconductor substrate;
a first electrode disposed on the device region and connected to the input portion or the output portion; and
a second electrode comprising a metal layer and disposed on the edge portion of the semiconductor layer so as to be on and in contact with the impurity region, the second electrode being connected to the input portion or the output portion which is not connected to the first electrode.
2. The discrete semiconductor element of claim 1 , wherein the second electrode surrounds the first electrode without any break.
3. The discrete semiconductor element of claim 1 , further comprising a third electrode disposed between the first and second electrodes and connected to the device region.
4. The discrete semiconductor element of claim 1 , further comprising an impurity region of a second general conductivity type formed in the semiconductor layer so as to be disposed between the device region and the second electrode.
5. The discrete semiconductor element of claim 1 , further comprising a first bump electrode formed on the first electrode and a second bump electrode formed on the second electrode.