Semiconductor device, semiconductor package for use therein, and manufacturing method thereof
View Patent ↗A semiconductor package includes a substrate for mounting and fixing a semiconductor chip thereon and a connecting pattern. The substrate is provided with an elongate opening formed therein. The semiconductor chip is fixed with its surface being mounted on the substrate and with its electrode being aligned within the elongate opening. The electrode of the semiconductor chip is electrically connected to the connecting pattern via wires through the elongate opening. The elongate opening and the wires are sealed with resin.
1. A semiconductor device comprising:
a substrate having a first surface and a second surface opposed to the first surface, said substrate further having an elongate opening defined therethrough from the first surface to the second surface;
a plurality of connecting patterns located on the second surface of said substrate, each of said plurality of connecting patterns having a wire connecting portion;
a semiconductor chip having a surface;
a tape bonding material, said semiconductor chip is mounted to the first surface of said substrate via said tape bonding material;
a plurality of electrodes located on the surface of said semiconductor chip and aligned with the elongate opening of said substrate;
a plurality of wires extending within the elongate opening of said substrate, first ends of said plurality of wires being respectively bonded to said plurality of electrodes, and second ends of said plurality of wires being respectively bonded to corresponding ones of the wire connecting portions of said plurality of connecting patterns;
a resist which covers the second surface of said substrate and said plurality of connecting patterns, wherein the wire connecting portions of said plurality of connecting patterns are exposed from said resist; and
a resin which covers said plurality of electrodes, said plurality of wires, and the wire connecting portions of said plurality of connecting patterns.
2. The semiconductor device of claim 1 , wherein the tape base material of said bonding material is polyimide.
3. The semiconductor device of claim 1 , wherein the material of said substrate is glass epoxy resin.
4. The semiconductor device of claim 1 , wherein said resist has an opening at which the wire connecting portions of said plurality of connecting patterns are located.
5. The semiconductor device of claim 1 , wherein each of said plurality of connecting patterns has an external connecting portion exposed from said resist.
6. The semiconductor device of claim 5 , further comprising a plurality of external connecting patterns respectively bonded to the external connecting portions of said plurality of connecting patterns.
7. The semiconductor device of claim 5 , wherein said resist has openings at which external connecting portions of said plurality of connecting patterns are respectively located.
8. The semiconductor device of claim 1 , wherein the elongate opening is smaller than said semiconductor chip.
9. The semiconductor device of claim 6 , wherein said resist extends out of elongate opening beyond a height of said plurality of external connecting terminals are bonded.
10. A semiconductor device comprising:
a substrate having a first surface and a second surface opposed to the first surface, said substrate further having an elongate opening defined therethrough from the first surface to the second surface;
a plurality of connecting patterns located on the second surface of said substrate, each of said plurality of connecting patterns having a wire connecting portion;
a semiconductor chip having a surface which is mounted to the first surface of said substrate;
a plurality of electrodes located on the surface of said semiconductor chip and aligned with the elongate opening of said substrate;
a plurality of wires extending within the elongate opening of said substrate, first ends of said plurality of wires being respectively bonded to said plurality of electrodes, and second ends of said plurality of wires being respectively bonded to corresponding ones of the wire connecting portions of said plurality of connecting patterns;
a resist which covers the second surface of said substrate and said plurality of connecting patterns, wherein the bonding portions of said plurality of connecting patterns are exposed from said resist; and
a resin which covers said plurality of electrodes, said plurality of wires, and the bonding portions of said plurality of connecting patterns, the resin having a surface consisting of a flat portion and a slope portion surrounding the flat portion.
11. The semiconductor device of claim 10 , wherein the material of said substrate is glass epoxy resin.
12. The semiconductor device of claim 10 , wherein said resist has an opening at which the wire connecting portions of said plurality of connecting patterns are located.
13. The semiconductor device of claim 10 , wherein each of said plurality of connecting patterns has an external connecting portion exposed from said resist.
14. The semiconductor device of claim 13 , further comprising a plurality of external connecting patterns respectively bonded to the external connecting portions of said plurality of connecting patterns.
15. The semiconductor device of claim 13 , wherein said resist has openings at which external connecting portions of said plurality of connecting patterns are respectively located.
16. The semiconductor device of claim 10 , wherein the elongate opening is smaller than said semiconductor chip.
17. The semiconductor device of claim 15 , wherein said resist extends out of elongate opening beyond a height of said plurality of external connecting terminals are bonded.