Non-volatile memory device, non-volatile memory system and control method for the non-volatile memory device in which driving ability of a selector transistor is varied
The control method includes a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within a memory block.
1. A non-volatile memory device comprising plural memory cells connected in series,
wherein a unit of memory block with the plural memory cells is defined by a boundary at which address allocation regularity of the plural memory cells changes from a shifting manner to a mirroring manner, and
the non-volatile memory device further comprises a control circuit which varies driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within the memory block.
2. A non-volatile memory device according to claim 1 , wherein the selector transistor selects:
a first diffusion layer of the selected memory cell and a second diffusion layer of the non-selected memory cell; or
a second diffusion layer of the selected memory cell and a first diffusion layer of the non-selected memory cell.
3. A non-volatile memory device according to claim 2 , wherein the selector transistor connects:
both a target bit line to be connected to a target diffusion layer which is targeted when a burst access readout operation is applied to either the first diffusion layer or the second diffusion layer and at least one adjoining target bit line which adjoins to the target bit line to a first potential; and
a non-target bit line which exists in a memory cell inclusive of the target diffusion layer and connected to a non-target diffusion layer to be paired with the target diffusion layer to a second potential.
4. A non-volatile memory device according to claim 1 , wherein the control circuit comprises a decoder which detects a predetermined address.
5. A non-volatile memory device according to claim 4 , wherein the predetermined address corresponds to a most significant bit.
6. A non-volatile memory device according to claim 4 , wherein the predetermined address corresponds to a point at which the address allocation regularity is switched to the mirroring manner from the shifting manner.
7. A non-volatile memory device according to claim 1 , wherein the control circuit comprises an internal power supply circuit which comprises:
a main power supply circuit which supplies main electric power during a burst access readout operation; and
a sub power supply circuit which supplies sub electric power in addition to the main electric power in response to a detection operation to be taken when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within the memory block.
8. A non-volatile memory device according to claim 7 , wherein the main power supply circuit comprises plural charge pumps which are controlled respectively at opposite phase in response to a least significant bit of an address signal.
9. A non-volatile memory device according to claim 7 , wherein the sub power supply circuit comprises a charge pump which is controlled in response to the detection operation.
10. A non-volatile memory device according to claim 1 , wherein the selector transistor corresponds to a column selector switch.
11. A non-volatile memory device according to claim 1 ,
wherein each of the plural memory cells comprises a first diffusion layer, a second diffusion layer, and an insulating trap layer which comprises a first trap region and second trap region adjoining to the first diffusion layer and the second diffusion layer, respectively, for trapping charges,
the plural memory cells being connected to one another in such a manner that, between two memory cells adjoining to each other, a first diffusion layer of one of the two memory cells and a second diffusion layer of other one of the two memory cells are connected to a bit line,
the non-volatile memory device further comprises:
a selector circuit connects: both a target bit line to be connected to a target diffusion layer which is targeted when a burst access readout operation is applied to either the first diffusion layer or the second diffusion layer and at least one adjoining target bit line which adjoins to the target bit line to a first potential; and a non-target bit line which exists in a memory cell inclusive of the target diffusion layer and connected to a non-target diffusion layer to be paired with the target diffusion layer to a second potential;
a detector circuit which detects that a readout access makes transition from a memory cell at one end to a memory cell at other end within the memory block during the burst access readout operation; and
an internal power supply circuit of which supply ability to supply electric power to the selector circuit is increased depending on a detection result of the detector circuit.
12. A control method of a non-volatile memory device comprising plural memory cells connected in series,
when a unit of memory block in the plural memory cells is defined by a boundary at which address allocation regularity of the plural memory cells changes from a shifting manner to a mirroring manner,
the control method comprising a step of varying driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within the memory block.
13. A non-volatile memory system comprising:
plural memory blocks each of which is a unit defined by a boundary at which address allocation regularity of the plural memory cells connected in series changes from a shifting manner to a mirroring manner; and
a control circuit which varies driving ability of a selector transistor which selects a diffusion layer in a selected memory cell and a diffusion layer of at least one non-selected memory cell which adjoins to the selected memory cell when the selected memory cell makes transition from a memory cell at one end to a memory cell at other end within the memory block.