Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation
View Patent ↗Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated peripheral circuitry formation are provided. Strips of charge storage material elongated in a row direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. Forming the strips defines the dimension of the resulting charge storage structures in the column direction. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. Strips of control gate material are formed between strips of charge storage material adjacent in the column direction. The strips of charge storage and control gate material are divided along their lengths in the row direction as part of forming isolation trenches and columns of active areas. After dividing the strips, the charge storage material at the peripheral circuitry region of the substrate is etched to define a gate dimension in the column direction for a peripheral transistor. Control gate interconnects can be formed to connect together rows of isolated control gates to extrinsically form word lines.
1. A method of making non-volatile memory, comprising:
forming a first layer of charge storage material at a peripheral circuitry region of a substrate and a memory array region of the substrate;
forming a second layer of charge storage material at the peripheral circuitry region and the memory array region;
etching the first layer at the array region to form a first set of strips of charge storage material elongated in a first direction with spaces therebetween in a second direction substantially perpendicular to the first direction;
etching the second layer at the array region to form a second set of strips of charge storage material elongated in the first direction with spaces therebetween in the second direction;
forming a third set of strips of conductive material elongated in the first direction and at least partially occupying the spaces between adjacent strips of the second layer of charge storage material;
etching the first set of strips, the second set of strips and the third set of strips along their lengths in the first direction thereby forming a set of first charge storage regions from each strip of the first set, a set of second charge storage regions from each strip of the second set and a set of control gates from each strip of the third set;
etching the first layer of charge storage material and the second layer of charge storage material at the peripheral circuitry region to define a dimension of a gate region for a transistor after etching the sets of strips at the memory array region, the gate region including a portion of the first layer of charge storage material and a portion of the second layer of charge storage material.
2. The method of claim 1 , wherein:
the first layer of charge storage material is undoped polysilicon; and
the second layer of charge storage material is doped polysilicon.