Semiconductor package and method for manufacturing thereof
A semiconductor package, which includes: a first substrate, on which a pre-designed pattern is formed; a first chip, mounted by a flip chip method on one side of the first substrate; a first molding, covering the first substrate and the first chip; a first via, which penetrates the first molding, and which is electrically connected with the pattern formed on the first substrate; an interposer, which is placed on the first molding, and on both sides of which a pre-designed pattern is formed respectively; a second via, penetrating the interposer and electrically connecting both sides of the interposer; a second substrate, placed on the interposer with at least one conductive ball positioned in-between, such that the second substrate is electrically connected with the pattern formed on the interposer; and a second chip mounted on the second substrate, can be used to improve heat release and increase the degree of integration.
1. A semiconductor package comprising:
a first substrate having a pre-designed pattern formed thereon;
a first chip mounted by a flip chip method on one side of the first substrate;
a first molding covering the first substrate and the first chip;
a first via penetrating the first molding and electrically connected with the pattern formed on the first substrate;
an interposer placed on the first molding and having a pre-designed pattern formed respectively on both sides thereof;
a second via penetrating the interposer and electrically connecting both sides of the interposer;
a second substrate placed on the interposer with at least one conductive ball positioned in-between such that the second substrate is electrically connected with the pattern formed on the interposer; and
a second chip mounted on the second substrate.
2. The semiconductor package of claim 1 , wherein the interposer is a metal oxide layer.
3. The semiconductor package of claim 2 , wherein the interposer is made of aluminum oxide (Al 2 O 3 ).
4. The semiconductor package of claim 1 , further comprising:
a passive component mounted on the first substrate.
5. The semiconductor package of claim 1 , wherein the first via is a solder bump.
6. The semiconductor package of claim 1 , wherein the second chip is connected to the second substrate by a wire bonding method,
and the semiconductor package further comprises a second molding covering the second chip and the second substrate.
7. The semiconductor package of claim 1 , further comprising:
a plurality of conductive balls formed on the other side of the first substrate.