Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus

1. A data output clock generating circuit for a semiconductor memory apparatus, comprising:

a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output clock; and

a falling data output clock generating unit configured to combine the falling clock with a falling clock extraction signal generated in response to a falling output enable signal and the rising clock, to generate a falling data output clock;

wherein the rising data output clock generating unit and the falling data output clock generating unit are independently driven in parallel,

wherein the rising data output clock generating unit is configured to generate the rising clock extraction signal being enabled at a time of a first rising edge of the falling clock after the rising output enable signal is enabled and being disabled at a time of a first rising edge of the falling clock after the rising output enable signal is disabled.

2. The data output clock generating circuit of claim 1 ,

wherein the rising data output clock generating unit is configured to extract the rising clock during a period when the rising clock extraction signal is enabled to generate the rising data output clock.

3. The data output clock generating circuit of claim 2 ,

wherein the rising data output clock generating unit includes:

a rising clock extraction signal generating section configured to receive the rising output enable signal and the falling clock to generate the rising clock extraction signal; and

a rising data output clock generating section configured to receive the rising clock extraction signal and the rising clock to generate the rising data output clock.

4. The data output clock generating circuit of claim 3 ,

wherein the rising clock extraction signal generating section includes:

an input section configured to receive the rising output enable signal and the falling clock to generate a set signal and a reset signal; and

a flip-flop configured to receive the set signal and the reset signal to generate the rising clock extraction signal.

5. The data output clock generating circuit of claim 1 ,

wherein the falling data output clock generating unit is configured to generate the falling clock extraction signal being enabled at a time of a first rising edge of the rising clock after the falling output enable signal is enabled and being disabled at a time of a first rising edge of the rising clock after the falling output enable signal is disabled.

6. The data output clock generating circuit of claim 5 ,

wherein the falling data output clock generating unit is configured to extract the falling clock during a period when the falling clock extraction signal is enabled to generate the falling data output clock.

7. The data output clock generating circuit of claim 6 ,

wherein the falling data output clock generating unit includes:

a falling clock extraction signal generating section configured to receive the falling output enable signal and the rising clock to generate the falling clock extraction signal; and

a falling data output clock generating section configured to receive the falling clock extraction signal and the falling clock to generate the falling data output clock.

8. The data output clock generating circuit of claim 7 ,

wherein the falling clock extraction signal generating section includes:

an input section configured to receive the falling output enable signal and the rising clock to generate a set signal and a reset signal; and

a flip-flop configured to receive the set signal and the reset signal to generate the falling clock extraction signal.