Semiconductor device and manufacturing method of the same
View Patent ↗A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.
1. A semiconductor device comprising:
a first wiring layer disposed on a semiconductor substrate;
a first insulating layer disposed on the first wiring layer and having a first opening formed therein;
a first metal layer embedded in the first opening so as to be connected to the first wiring layer;
a second wiring layer disposed on the first insulating layer so as to be connected to the first metal layer;
a second insulating layer disposed on the second wiring layer and the first insulating layer and having a second opening formed therein, the second opening covering the first opening;
a third wiring layer disposed on the second insulating layer so as to be connected to the second wiring layer through the second opening; and
an alloy layer disposed between the second and third wiring layers and made of metals of the second and third wiring layers, the alloy layer being formed non-uniformly between the second and third wiring layers so that the alloy layer is formed above the first opening but is not formed horizontally away from the first opening.
2. The semiconductor device of claim 1 , wherein the second wiring connected to the first metal layer is configured to operate as an electrode.
3. A semiconductor device comprising:
a first wiring layer disposed on a semiconductor substrate;
a first insulating layer disposed on the first wiring layer and having a first opening formed therein;
a first metal layer embedded in the first opening so as to be connected to the first wiring layer;
a second wiring layer disposed on the first insulating layer so as to be connected to the first metal layer;
a second insulating layer disposed on the second wiring layer and the first insulating layer and having a second opening formed therein, the second opening covering the first opening;
a third wiring layer disposed on the second insulating layer so as to be connected to the second wiring layer through the second opening; and
an alloy layer disposed between the second and third wiring layers and made of metals of the second and third wiring layers,
wherein the third wiring layer comprises a chromium layer and a copper layer disposed on the chromium layer, grains of a first portion of the chromium layer located directly above the first metal layer are more loosely packed than grains of a second portion of the chromium layer located not directly above the first metal layer so that the grains of the first portion have wider spaces between them than the grains of the second portion, and the alloy layer is formed in the wider spaces among the grains of the first portion of the chromium layer.
4. The semiconductor device of claim 3 , wherein the second wiring layer comprises a barrier metal layer and a second metal layer formed on the barrier metal layer, in the first opening the barrier metal layer is disposed at a bottom of the first opening with the first metal layer covering the barrier metal layer, the second metal layer is in contact with the first metal layer, and the first portion of the chromium layer is in contact with the second metal layer in contact with the first metal layer.
5. The semiconductor device of claim 4 , wherein the first metal layer comprises tungsten, and the second metal layer comprises aluminum or an aluminum alloy.
6. The semiconductor device of claim 5 , wherein the copper layer in the third wiring layer comprises a copper plated layer.
7. The semiconductor device of claim 4 , wherein the second insulating layer comprises a polybenzoxazole film or a polyimide resin film.
8. The semiconductor device of claim 3 , wherein the second wiring connected to the first metal layer is configured to operate as an electrode.
9. A semiconductor device comprising:
a first wiring layer disposed on a semiconductor substrate;
a first insulating layer disposed on the first wiring layer and having a plurality of first openings formed therein;
a barrier metal film comprising titanium, covering bottoms and sidewalls of the first openings and covering a top portion of the first insulating layer;
a plurality of first metal layers comprising tungsten and embedded in corresponding first openings covered by the barrier metal film;
a second metal layer comprising aluminum and in contact with the first metal layers embedded in the first openings and in contact with the barrier metal layer disposed on the top portion of the first insulating layer;
a second insulating layer disposed on the second metal layer and the first insulating layer and having a second opening formed therein, the second opening covering the first openings;
a third metal layer comprising chromium disposed in the second opening so as to be in contact with the second metal layer; and
a fourth metal layer comprising copper and in contact with the third metal layer in the second opening,
wherein an alloy layer made of the metals of the second and fourth metal layers is formed non-uniformly in the third metal layer so that the alloy layer is formed above the first opening but is not formed horizontally away from the first opening.