IP Library Granted Patent US 7,935,575
Granted Patent B2
US 7,935,575 · App. 12/098,813 · Granted May 3, 2011

Method of forming a semiconductor package and structure therefor

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Quick Facts
Patent No.
US 7,935,575
App. No.
12/098,813
Granted
May 3, 2011
Kind
B2
Abstract

In one embodiment, a semiconductor package is formed to include a leadframe that includes a plurality of die attach areas for attaching a semiconductor die to the leadframe. The leadframe is positioned to overlie another leadframe that forms some of the external terminals or leads of the package.

Claims (19)

1. A method of forming a semiconductor package comprising:

forming a first leadframe of the semiconductor package having a plurality of die attach areas on a first surface of the first leadframe wherein the plurality of die attach areas are separated from each other by a recess in the first surface including forming a support element of the first leadframe extending away from the first surface at a first angle;

forming a second leadframe of the semiconductor package having a plurality of contact pads for electrically contacting electrodes of a semiconductor die wherein the electrodes are on a first surface of the semiconductor die including forming the second leadframe having a positioning element with a positioning feature that is formed to mate with the support element of the first leadframe;

attaching the semiconductor die to a first die attach area of the plurality of die attach areas with a die attachment material;

positioning the first leadframe over the second leadframe with the support element of the first leadframe mating with the positioning feature to position the electrodes of the semiconductor die to overlie at least a portion of the plurality of contact pads of the second leadframe;

attaching the first and second contact pads of the second leadframe to the electrodes of the semiconductor die; and

encapsulating the first and second leadframes with an encapsulating material wherein a portion of the plurality of contact pads are exposed to form first and second leads of the semiconductor package and wherein a distal end of the support element is exposed to form a third lead of the semiconductor package.

2. The method of claim 1 wherein attaching the semiconductor die to the first die attach area includes attaching the semiconductor die to more than one die attach area of the plurality of die attach areas.

3. The method of claim 1 wherein positioning the first leadframe includes placing an electrically conducting attachment material on the plurality of contact pads prior to the positioning step, and

wherein attaching the plurality of contact pads includes curing the electrically conducting attachment material.

4. The method of claim 1 wherein no attachment material is used to attach the support element to the positioning element or to the positioning feature during the step of positioning the first leadframe over the second leadframe.

5. The method of claim 1 wherein forming the first leadframe includes forming the first leadframe with a plurality of support elements extending away from the first surface at an angle that is less than one hundred eighty degrees to the first surface.

6. A method of forming a semiconductor package comprising:

forming a first leadframe of the semiconductor package having a plurality of die attach areas on a first surface of the first leadframe wherein the plurality of die attach areas are formed to be attached to a single semiconductor die and wherein the plurality of die attach areas are separated from each other and from the first surface by a recess to prevent die attachment material from bridging between the plurality of die attach areas including forming a support element of the first leadframe extending away from the first surface at a first angle; and

forming a second leadframe of the semiconductor package having a plurality of contact pads for electrically contacting electrodes of the single semiconductor die wherein the second leadframe is configured to underlie the first leadframe including forming the second leadframe having a positioning element with a positioning feature that is formed to mate with the support element of the first leadframe.

7. The method of claim 6 further including encapsulating the first and second leadframes with an encapsulating material wherein a portion of a first and second contact pads of the plurality of contact pads are exposed to form first and second leads of the semiconductor package and wherein a distal end of the support element is exposed to form a third lead of the semiconductor package.

8. The method of claim 6 wherein forming the second leadframe having the positioning element with the positioning feature that is formed to mate with the support element of the first leadframe includes forming the positioning feature to surround three sides of the support element and expose a distal end of the support element.

9. The method of claim 8 further including encapsulating the first and second leadframes wherein the positioning feature is not attached to the support element with an attachment material prior to the encapsulating step.

10. The method of claim 6 further including encapsulating the first and second leadframes wherein at least a portion of the second surface of the first leadframe is exposed after the encapsulating is complete.

Assignments (2)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →