Security element for an integrated circuit, integrated circuit including the same, and method for securing an integrated circuit
View Patent ↗An integrated circuit including a substrate; a circuit pattern formed over the substrate; and one or more fences formed around edges of the circuit pattern, each of the one or more fences having a determined electrical resistance which is used to detect the addition of malicious circuitry. Each fence has a determined electrical resistance which is used to monitor the validity of the fence.
1. A method of securing an integrated circuit having a circuit pattern, comprising the steps of:
analyzing design data for the circuit pattern to determine edges of the circuit pattern;
determining a route that surrounds the edges of the circuit pattern;
forming a fence along the route, wherein the fence has a determined electrical resistance; and
detecting a change in the electrical resistance of the fence so as to determine an alteration of the fence.
2. The method of claim 1 , wherein the step of analyzing comprises dividing the design data into partitions.
3. The method of claim 2 , wherein the step of analyzing comprises determining which partitions are too close together to accommodate circuitry.
4. The method of claim 3 , further comprising a step of merging the partitions that are too close together to accommodate circuitry.
5. The method of claim 1 , wherein the step of determining the route comprises applying a set of rules to ensure that the route provides at least a minimum clearance from the edges of the circuit pattern.
6. The method of claim 1 , wherein the step of forming a fence comprises forming the fence in a polygon format.
7. The method of claim 1 , wherein the step of forming a fence further comprises generating layout data for the fence.
8. The method of claim 7 , wherein the layout data is generated using a set of rules.
9. The method of claim 1 , wherein the step of forming a fence comprises maintaining a running sum of electrical resistances for the fence.