Ferroelectric register, and method for manufacturing capacitor of the same
View Patent ↗The present invention discloses a ferroelectric register and a method for manufacturing a capacitor of the same. The ferroelectric register is configured to reduce probability of data storage failure due to a weak state capacitor, by connecting a plurality of capacitors in parallel in a ferroelectric capacitor unit for storing data, instead of using a single capacitor, thereby improving storage reliability and stability. In addition, the ferroelectric register obtains a data sensing margin by pumping a cell plate signal into not a power voltage level but a pumping voltage level.
1. A method for manufacturing a ferroelectric capacitor of a ferroelectric register, which includes a pull-up switch for outputting a power voltage when a pull-up enable signal is activated; a pull-up driving unit for receiving the power voltage from the pull-up switch, and for pulling up a voltage of a data storage node to the power voltage; a write enable control unit for transmitting a differential data to the data storage node according to a write control signal; the ferroelectric capacitor connected between the data storage node and a plate line and storing the differential data when a cell plate signal from the plate line is activated; a pull-down switch for transmitting a ground voltage to the data storage node when a pull-down enable signal is activated; and a pull-down driving unit for receiving the ground voltage from the pull-down switch and for pulling down the voltage of the data storage node to the ground voltage, comprising:
a first process for forming a contact plug on a bit line;
a second process for sequentially stacking a first electrode layer, a first ferroelectric layer, a second electrode layer, a second ferroelectric layer and a third electrode layer on the contact plug; and
a third process for electrically connecting the bit line to the third electrode layer by forming a metal line, which has one end connected to the third electrode and the other end connected to the bit line,
wherein the bit line is electrically connected with the data storage node and the second electrode layer is electrically connected with the plate line.
2. The method of claim 1 , wherein the metal line has one end that is directly connected to the third electrode and the other end directly connected to the bit line.