IP Library Granted Patent US 7,969,007
Granted Patent B2
US 7,969,007 · App. 12/111,383 · Granted Jun 28, 2011

Semiconductor device and manufacturing method thereof

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Quick Facts
Patent No.
US 7,969,007
App. No.
12/111,383
Granted
Jun 28, 2011
Kind
B2
Abstract

A semiconductor device with improved moisture resistance and its manufacturing method as well as a manufacturing method of a semiconductor device which simplifies a manufacturing process and improves productivity are offered. This invention offers a CSP type semiconductor device and its manufacturing method that can prevent moisture and the like from infiltrating into it to attain high reliability by covering a side surface of a semiconductor chip with a thick protection layer. This invention also offers a highly productive manufacturing method of semiconductor devices by which a supporter bonded to semiconductor dice is etched from a back surface-side of the supporter so that the semiconductor devices can be separated without dicing.

Claims (31)

1. A semiconductor device comprising:

a semiconductor substrate comprising a circuit element formed in a top surface thereof;

a first insulation film disposed on the top surface of the semiconductor substrate;

a metal pad connected to the circuit element and disposed at least partially on the first insulation film adjacent a lateral edge of the top surface;

a second insulation film disposed on a side surface and a bottom surface of the semiconductor substrate;

a metal wiring disposed on the second insulation film so as to be connected to a bottom portion of the metal pad, the metal wiring extending from the bottom surface to the side surface of the semiconductor substrate;

a protection layer covering the metal wiring so that a thickness of an edge portion of the protection layer is larger than a sum of thicknesses of the semiconductor substrate, the first and second insulation films and the metal wiring; and

a conductive terminal connected to the metal wiring through an opening formed in the protection layer.

2. A semiconductor device comprising:

a semiconductor substrate comprising a circuit element formed in a top surface thereof;

a first insulation film disposed on the top surface of the semiconductor substrate;

a metal pad connected to the circuit element and disposed at least partially on the first insulation film adjacent a lateral edge of the top surface;

a second insulation film disposed on a side surface and a bottom surface of the semiconductor substrate;

a metal wiring disposed on the second insulation film so as to be connected to a bottom portion of the metal pad, the metal wiring extending from the bottom surface to the side surface of the semiconductor substrate;

a protection layer comprising a first protection layer and a second protection layer and covering the metal wiring so as to make a surface of the protection layer flat at the metal pad; and

a conductive terminal connected to the metal wiring through an opening formed in the protection layer.

3. The semiconductor device of claim 1 , further comprising a supporter bonded to the top surface of the semiconductor substrate so as to cover the top surface of the semiconductor substrate and the metal pad.

4. A semiconductor device comprising:

a first semiconductor device comprising a semiconductor substrate comprising a circuit element formed in a top surface thereof, a first insulation film disposed on the top surface of the semiconductor substrate, a metal pad connected to the circuit element and disposed at least partially on the first insulation film adjacent a lateral edge of the top surface, a second insulation film disposed on a side surface and a bottom surface of the semiconductor substrate, a metal wiring disposed on the second insulation film so as to be connected to a bottom portion of the metal pad and extending from the bottom surface to the side surface of the semiconductor substrate, a protection layer covering the metal wiring, and a conductive terminal connected to the metal wiring through an opening formed in the protection layer; and

a second semiconductor device comprising a metal pad formed on a top surface thereof,

wherein the first semiconductor device is stacked on the second semiconductor device so that the conductive terminal of the first semiconductor device is in contact with the metal pad of the second semiconductor device and that an edge portion of the protection layer is in contact with the top surface of the second semiconductor device.

5. A semiconductor device comprising:

a semiconductor substrate comprising a circuit element formed in a top surface thereof;

a first insulation film disposed on the top surface of the semiconductor substrate;

a metal pad connected to the circuit element and disposed at least partially on the first insulation film adjacent a lateral edge of the top surface;

a second insulation film disposed on a side surface and a bottom surface of the semiconductor substrate;

a metal wiring disposed on the second insulation film so as to be connected to a bottom portion of the metal pad, the metal wiring extending from the bottom surface to the side surface of the semiconductor substrate;

a protection layer disposed on the metal wiring;

a conductive terminal connected to the metal wiring through an opening formed in the protection layer; and

a conductive film disposed on the protection layer so as to make a surface of the conductive film flat on the metal pad.

6. The semiconductor device of claim 5 , further comprising a supporter bonded to the top surface of the semiconductor substrate so as to cover the top surface of the semiconductor substrate and the metal pad.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2008
From: NOMA, TAKASHI; SHINOGI, HIROYUKI; OKUBO, NOBORU
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 021173/0359 →