Multi-voltage electrostatic discharge protection
An electrostatic discharge (ESD) clamp ( 41, 51, 61, 71, 81, 91 ), coupled across input-output (I/O) ( 22 ) and common (GND) ( 23 ) terminals of a protected semiconductor SC device or IC ( 24 ), comprises, an ESD transistor (ESDT) ( 25 ) with source-drain ( 26, 27 ) coupled between the GND ( 23 ) and I/O ( 22 ), a first resistor ( 30 ) coupled between gate ( 28 ) and source ( 26 ) and a second resistor ( 30 ) coupled between ESDT body ( 29 ) and source ( 26 ). Paralleling the resistors ( 30, 32 ) are control transistors ( 35, 35′ ) with gates ( 38, 38′ ) coupled to one or more bias supplies Vb, Vb′. The main power rail (Vdd) of the device or IC ( 24 ) is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vt 1 is low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vt 1 rises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT ( 25 ) during normal operation is much reduced.
1. An electronic device embodying an electrostatic discharge (ESD) clamp coupled across first and second terminals of a protected semiconductor device or integrated circuit included in the electronic device, comprising:
a first ESD transistor with source, drain, gate and body, wherein the source of the first ESD transistor is coupled to the second terminal and the drain of the first ESD transistor is coupled to the first terminal;
a first resistor coupled between the gate and the source of the first ESD transistor;
a second resistor coupled between the body and the source of the first ESD transistor; and
first and second control transistors having sources, drains and gates, wherein the source and drain of the first control transistor are coupled in parallel with the first resistor and the gate of the first control transistor is adapted to be coupled to a first bias voltage, and the source and drain of the second control transistor are coupled in parallel with the second resistor and the gate of the second control transistor is adapted to be coupled to a second bias voltage such that the first and second bias voltages can be adjusted to change the impedance between the second terminal and the gate of the first ESD transistor and the impedance between the second terminal and the body of the first ESD transistor to actively control the activation voltage of the first ESD transistor during operation of the electronic device.
2. The electronic device of claim 1 , further comprising:
a second ESD transistor with source, drain, gate and body, wherein the source and drain of the second ESD transistor are serially coupled between the source of the first ESD transistor and the second terminal;
a third resistor coupled between the gate and the source of the second ESD transistor;
a fourth resistor coupled between the body and the source of the second ESD transistor; and
third and fourth control transistors having sources, drains and gates, wherein the source and drain of the third control transistor are coupled in parallel with the third resistor and the gate of the third control transistor is adapted to be coupled to a third bias voltage, and the source and drain of the fourth control transistor are coupled in parallel with the fourth resistor and the gate of the fourth control transistor is adapted to be coupled to a fourth bias voltage.
3. The electronic device of claim 2 , wherein the drain of the second ESD transistor is coupled to the source of the first ESD transistor.
4. The electronic device of claim 2 , wherein the source of the second ESD transistor is coupled to the source of the first ESD transistor.
5. The electronic device of claim 1 , wherein the first and second bias voltages are derived from Vdd, where Vdd is the main power rail voltage of the protected semiconductor device or integrated circuit.
6. The electronic device of claim 1 , further comprising one or more low pass filters between sources of the first and second bias voltages and the gates of the first and second control transistors.
7. The electronic device of claim 6 , wherein the first and second bias voltages are derived from a common source and a single low pass filter is provided between the common source and the gates of the first and second control transistors.
8. The electronic device of claim 6 , wherein the one or more low pass filters substantially pass signals of frequency less than about 800 mega-Hertz and substantially attenuate signals above about 800 mega-hertz.
9. The electronic device of claim 6 , wherein the one or more low pass filters comprise:
a first capacitor with first and second terminals across an input to the filter;
a second capacitor with first and second terminals across an output to the filter; and
a further resistor coupling the first terminals of the first and second capacitors.
10. The electronic device of claim 6 , wherein the one or more low-pass filters each have input terminals and output terminals and the filters comprise:
a capacitor with first and second terminals, wherein one of the first or second terminals of the capacitor is coupled to one of the input or output terminals of the filter; and
a further resistor couples an other of the first or second terminals of the capacitor to an other of the input or output terminals of the filter.
11. The electronic device of claim 1 , wherein the first bias voltage is less than a gate breakdown voltage of the first control transistor and the second bias voltage is less than a gate breakdown voltage of the second control transistor.
12. The electronic device of claim 1 , wherein the electronic device is configured such that activation voltage of the first ESD transistor increases as the bias voltages applied to the first and second control transistors are increased.
13. An electronic device, comprising:
an electrostatic discharge (ESD) transistor having a source, a drain, a gate, and a body, the drain and source of the ESD transistor configured to be coupled first and second potentials, respectively;
a first control transistor having a source, a drain, and a gate, the drain of the first control transistor coupled to the gate of the ESD transistor, and the source of the first control transistor configured to be coupled to the second potential;
a second control transistor having a source, a drain, and a gate, the drain of the second control transistor coupled to the body of the ESD transistor, and the source of the second control transistor configured to be coupled to the second potential;
a first resistor coupled to the gate of the ESD transistor and configured to be coupled to the second potential, the first resistor coupled in parallel with the first control transistor;
a second resistor coupled to the drain of the ESD transistor and configured to be coupled to the second potential, the second resistor coupled in parallel with the second control transistor; and
first and second bias terminals coupled to the gates of the first and second control transistors, respectively, and configured to receive first and second bias voltages during operation of the electronic device;
wherein the first and second control transistors are configured (i) to reside in an OFF state and impart the ESD transistor with a first predetermined activation voltage when the first and second bias voltages have a predetermined low value, and (ii) to switch to an ON state and impart the ESD transistor with a second predetermined activation voltage greater than the first predetermined activation voltage when the first and second bias voltages have a predetermined high value.
14. The electronic device of claim 13 , wherein the ESD transistor, the first and second resistors, the first and second control transistors, and the first and second bias terminals are included within a first ESD clamp of the electronic device, and wherein the electronic device further comprises:
first and second device terminals; and
a second ESD clamp coupled in series with the first ESD clamp between the first and second device terminals.
15. The electronic device of claim 13 , further comprising:
a first node to which the first resistor and the source of the first control transistor are coupled, the first node configured to be coupled to the second potential; and
a second node to which the second resistor and the source of the first control transistor are coupled, the second node configured to be coupled to the second potential.
16. The electronic device of claim 15 , further comprising a ground terminal coupled to the source of the first ESD transistor, to the first node, and to the second node.
17. The electronic device of claim 13 , further comprising:
a first low pass filter coupled to the gate of the first control transistor; and
a second low pass filter coupled to the gate of the second control transistor.
18. The electronic device of claim 17 , wherein the first low pass filter is coupled between the first bias terminal and the gate of the first control transistor, and wherein the second low pass filter is coupled between the second bias terminal and the gate of the second control transistor.
19. The electronic device of claim 17 , further comprising a ground terminal coupled to the source of the ESD transistor, to the first low pass filter, and to the second low pass filter.