Chip and wafer integration process using vertical connections
View Patent ↗A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.
1. A semiconductor structure comprising:
a first substrate having a first semiconductor device formed therein and having a top surface and a bottom surface;
a dielectric layer overlying the top surface of the first substrate, the dielectric layer having embedded therein an electrical conductor extending through the dielectric layer; and
a second substrate having a second semiconductor device formed therein, the second substrate overlying the dielectric layer so that the electrical conductor forms an electrical connection between the second semiconductor device and the first semiconductor device,
wherein:
at least one of the first substrate and the second substrate has an opening extending therethrough;
an electrical conductor is disposed in the opening and contacts the electrical conductor embedded in the dielectric layer, and
the electrical conductor disposed in the opening includes a unitary void formed therein
wherein with respect to the opening extending through at least one of the first substrate and the second substrate, the electrical conductor disposed in the opening fills the opening except for the unitary void so that a solid via with the unitary void is formed.
2. A semiconductor structure according to claim 1 , wherein
the dielectric layer includes a first layer having an electrical conductor extending therethrough and making contact with the first semiconductor device and a second layer having an electrical conductor extending therethrough and making contact with the second semiconductor device, and
the first layer and the second layer are joined by a stud/via interconnection to form said electrical connection.
3. A semiconductor structure according to claim 1 , wherein each of the first substrate and the second substrate has an opening extending therethrough with an electrical conductor disposed in the opening and contacting the electrical conductor embedded in the dielectric layer, thereby forming a conducting path from the bottom surface of the first substrate to a top surface of the second substrate.
4. A semiconductor structure according to claim 1 , further comprising a conducting pad on the bottom surface of the first substrate electrically connected to an electrical conductor disposed in an opening extending through the first substrate, so that said conducting pad is electrically connected to at least one of the first semiconductor device and the second semiconductor device.
5. A semiconductor structure according to claim 1 , wherein the first semiconductor device and the second semiconductor device are of different types.
6. A semiconductor structure according to claim 5 , wherein the different types of devices include DRAM devices and processor devices.
7. A semiconductor structure according to claim 1 , wherein the first substrate and the second substrate are of different materials.
8. A semiconductor structure according to claim 5 , wherein the first semiconductor device and the second semiconductor device form a vertically integrated device.
9. A semiconductor structure according to claim 1 , wherein at least one of the first substrate and the second substrate has a thickness not greater than about 100 μm.
10. A semiconductor structure comprising:
a first substrate having a first semiconductor device formed therein and having a top surface and a bottom surface;
a dielectric layer overlying the top surface of the first substrate, the dielectric layer having embedded therein an electrical conductor extending through the dielectric layer; and
a second substrate having a second semiconductor device formed therein, the second substrate overlying the dielectric layer so that the electrical conductor forms an electrical connection between the second semiconductor device and the first semiconductor device,
wherein:
at least one of the first substrate and the second substrate has an opening extending therethrough;
an electrical conductor is disposed in the opening and contacts the electrical conductor embedded in the dielectric layer, and
the electrical conductor disposed in the opening includes a unitary void formed therein
wherein with respect to the opening extending through at least one of the plurality of substrates, the electrical conductor formed in the opening fills the opening except for the unitary void so that a solid via with the unitary void is formed.
11. A semiconductor structure according to claim 10 , wherein
the dielectric layer includes a first layer having an electrical conductor extending therethrough and making contact with the first semiconductor device and a second layer having an electrical conductor extending therethrough and making contact with the second semiconductor device, and
the first layer and the second layer are joined by a stud/via interconnection to form said electrical connection.
12. A semiconductor structure according to claim 10 , wherein each of the first substrate and the second substrate has an opening extending therethrough with an electrical conductor disposed in the opening and contacting the electrical conductor embedded in the dielectric layer, thereby forming a conducting path from the bottom surface of the first substrate to a top surface of the second substrate.
13. A semiconductor structure according to claim 10 , further comprising a conducting pad on the bottom surface of the first substrate electrically connected to an electrical conductor disposed in an opening extending through the first substrate, so that said conducting pad is electrically connected to at least one of the first semiconductor device and the second semiconductor device.
14. A semiconductor structure according to claim 10 , wherein the first semiconductor device and the second semiconductor device are of different types.
15. A semiconductor structure according to claim 14 , wherein the different types of devices include DRAM devices and processor devices.
16. A semiconductor structure according to claim 10 , wherein the first substrate and the second substrate are of different materials.
17. A semiconductor structure according to claim 14 , wherein the first semiconductor device and the second semiconductor device form a vertically integrated device.
18. A semiconductor structure according to claim 10 , wherein at least one of the first substrate and the second substrate has a thickness not greater than about 100 μm.