IP Library Granted Patent US 7,957,924
Granted Patent B2
US 7,957,924 · App. 12/118,217 · Granted Jun 7, 2011

System and method for distortion analysis

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Quick Facts
Patent No.
US 7,957,924
App. No.
12/118,217
Granted
Jun 7, 2011
Kind
B2
Abstract

A method, circuit, and computer program product for receiving a first intermediate signal that is at least partially based upon a first reference signal. A second intermediate signal is received that is a time-shifted version of the first intermediate signal. An output signal is generated that is based upon the difference between the first intermediate signal and the second intermediate signal. An anticipated differential change in the output signal is determined, the anticipated differential change to occur based upon a transition in the first reference signal. A realized differential change in the output signal is measured, the realized differential change occurring based upon a transition in the first reference signal. The realized differential change in the output signal is compared to the anticipated differential change in the output signal to determine a nonlinearity indicator.

Claims (35)

1. A method comprising:

receiving, at a comparator, a first intermediate signal that is at least partially based upon a first reference signal;

receiving, at the comparator, a second intermediate signal that is a time-shifted version of the first intermediate signal;

generating, at the comparator, an output signal that is based upon the difference between the first intermediate signal and the second intermediate signal;

determining, at a processor, an anticipated differential change in the output signal, the anticipated differential change to occur based upon a transition in the first reference signal;

measuring, at the processor, a realized differential change in the output signal, the realized differential change occurring based upon a transition in the first reference signal; and

comparing, at the processor, the realized differential change in the output signal to the anticipated differential change in the output signal to determine a nonlinearity indicator.

2. The method of claim 1 wherein the first reference signal is a first digital reference signal.

3. The method of claim 2 wherein the first digital reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

4. The method of claim 3 wherein the device under test includes a digital-to-analog converter.

5. The method of claim 1 wherein the first reference signal is a first analog reference signal.

6. The method of claim 5 wherein the first analog reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

7. The method of claim 6 wherein the device under test includes an amplifier.

8. A circuit configured to perform operations comprising:

a comparator configured to receive a first intermediate signal that is at least partially based upon a first reference signal, the comparator further configured to receive a second intermediate signal that is a time-shifted version of the first intermediate signal, the comparator being further configured to generate an output signal that is based upon the difference between the first intermediate signal and the second intermediate signal; and

a processor configured to determine an anticipated differential change in the output signal, the anticipated differential change to occur based upon a transition in the first reference signal, the processor further configured to measure a realized differential change in the output signal, the realized differential change occurring based upon a transition in the first reference signal, the processor being further configured to compare the realized differential change in the output signal to the anticipated differential change in the output signal to determine a nonlinearity indicator.

9. The circuit of claim 8 wherein the first reference signal is a first digital reference signal.

10. The circuit of claim 9 wherein the first digital reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

11. The circuit of claim 10 wherein the device under test includes a digital-to-analog converter.

12. The circuit of claim 8 wherein the first reference signal is a first analog reference signal.

13. The circuit of claim 12 wherein the first analog reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

14. The circuit of claim 13 wherein the device under test includes an amplifier.

15. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:

receiving, at a comparator, a first intermediate signal that is at least partially based upon a first reference signal;

receiving, at a comparator, a second intermediate signal that is a time-shifted version of the first intermediate signal;

generating, at a comparator, an output signal that is based upon the difference between the first intermediate signal and the second intermediate signal;

determining, at a processor, an anticipated differential change in the output signal, the anticipated differential change to occur based upon a transition in the first reference signal;

measuring, at a processor, a realized differential change in the output signal, the realized differential change occurring based upon a transition in the first reference signal; and

comparing, at a processor, the realized differential change in the output signal to the anticipated differential change in the output signal to determine a nonlinearity indicator.

16. The computer program product of claim 15 wherein the first reference signal is a first digital reference signal.

17. The computer program product of claim 16 wherein the first digital reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

18. The computer program product of claim 17 wherein the device under test includes a digital-to-analog converter.

19. The computer program product of claim 15 wherein the first reference signal is a first analog reference signal.

20. The computer program product of claim 19 wherein the first analog reference signal is provided to a device under test such that the device under test generates the first intermediate signal.

21. The computer program product of claim 20 wherein the device under test includes an amplifier.

Assignments (10)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
RELEASE OF SECURITY INTEREST IN UNITED STATES PATENTS Recorded Dec 18, 2014
From: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
To: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
Reel/Frame 034660/0394 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
CHANGE OF NAME Recorded May 27, 2014
From: LTX-CREDENCE CORPORATION
To: XCERRA CORPORATION
Reel/Frame 033032/0768 →
SECURITY AGREEMENT Recorded Jan 17, 2014
From: LTX-CREDENCE CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 032086/0476 →
MERGER Recorded Mar 3, 2011
From: CREDENCE SYSTEMS CORPORATION
To: LTX-CREDENCE CORPORATION
Reel/Frame 025894/0629 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2008
From: LIGGIERO, RICHARD, III; REISS, ALAN J.
To: LTX CORPORATION
Reel/Frame 021372/0158 →