Pad current splitting
An integrated circuit with a monolithic semiconducting substrate formed in a chip, where the chip has a peripheral edge, a backside, and an opposing top on which circuitry is formed. A first ring of bonding pads is formed along at least a portion of the peripheral edge. At least one of the bonding pads is configured as a power pad, and at least one of the bonding pads is configured as a ground pad. An intermediate power bus is disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. An intermediate ground bus is also disposed interior to the first ring of bonding pads on the chip, and forms no direct electrical connections to any core devices. A power pad wire forms an exclusive electrical connection between the power pad and the intermediate power bus. A ground pad wire forms an exclusive electrical connection between the ground pad and the intermediate ground bus. A power strap forms an electrical connection between the intermediate power bus and a power mesh. A ground strap forms an electrical connection between the intermediate ground bus and a ground mesh.
1. An integrated circuit, comprising:
a monolithic semiconducting substrate formed in a chip, the chip having a peripheral edge, a backside, and an opposing top on which circuitry is formed,
a first ring of bonding pads formed along at least a portion of the peripheral edge, at least one of the bonding pads configured as a power pad and at least one of the bonding pads configured as a ground pad,
an intermediate power bus disposed interior to the first ring of bonding pads on the chip, the intermediate power bus forming no direct electrical connections to any core devices,
an intermediate ground bus disposed interior to the first ring of bonding pads on the chip, the intermediate ground bus forming no direct electrical connections to any core devices,
a power pad wire forming an exclusive electrical connection to the power pad at a first end of the power pad wire, and forming an electrical connection to the intermediate power bus at a second end of the power pad wire,
a ground pad wire forming an exclusive electrical connection to the ground pad at a first end of the ground pad wire, and forming an electrical connection to the intermediate ground bus at a second end of the ground pad wire,
a power strap forming an electrical connection to the intermediate power bus at a first end of the power strap, and forming an electrical connection to a power mesh at a second end of the power strap, and
a ground strap forming an electrical connection to the intermediate ground bus at a first end of the ground strap, and forming an electrical connection to a ground mesh at a second end of the ground strap.
2. The integrated circuit of claim 1 , wherein the first ring of bonding pads is formed in a contiguous pattern completely around the peripheral edge.
3. The integrated circuit of claim 1 , wherein the power pad comprises a plurality of power pads.
4. The integrated circuit of claim 1 , wherein the ground pad comprises a plurality of ground pads.
5. The integrated circuit of claim 1 , wherein a second ring of bonding pads is formed interior to the first ring of bonding pads, and the intermediate power bus and the intermediate ground bus are disposed exterior to the second ring of bonding pads.
6. The integrated circuit of claim 1 , wherein:
a second ring of bonding pads is formed interior to the first ring of bonding pads,
the intermediate power bus and the intermediate ground bus are disposed exterior to the second ring of bonding pads,
a plurality of power straps form electrical connections between the intermediate power bus and the power mesh,
a plurality of ground straps form electrical connections between the intermediate ground bus and the ground mesh,
exactly one of a power strap and a ground strap is disposed between each of the bonding pads of the second ring of bonding pads.
7. The integrated circuit of claim 1 , wherein a plurality of power pad wires form electrical connections between the power pads and the intermediate power bus.
8. The integrated circuit of claim 1 , wherein a plurality of ground pad wires form electrical connections between the ground pads and the intermediate ground bus.
9. The integrated circuit of claim 1 , wherein a plurality of power straps form electrical connections between the intermediate power bus and the power mesh.
10. The integrated circuit of claim 1 , wherein a plurality of ground straps form electrical connections between the intermediate ground bus and the ground mesh.
11. The integrated circuit of claim 1 , wherein neither the intermediate power bus nor the intermediate ground bus form any direct electrical connections to any IO devices.
12. An integrated circuit, comprising:
a monolithic semiconducting substrate formed in a chip, the chip having a peripheral edge, a backside, and an opposing top on which circuitry is formed,
a first ring of bonding pads formed in a contiguous pattern completely around the peripheral edge, a plurality of the bonding pads configured as power pads and a plurality of the bonding pads configured as ground pads,
an intermediate power bus disposed interior to the first ring of bonding pads on the chip, the intermediate power bus forming no direct electrical connections to any core devices,
an intermediate ground bus disposed interior to the first ring of bonding pads on the chip, the intermediate ground bus forming no direct electrical connections to any core devices,
power pad wires forming exclusive electrical connections to the power pads at first ends of the power pad wires, and forming electrical connections to the intermediate power bus at second ends of the power pad wires,
ground pad wires forming exclusive electrical connection to the ground pads at first ends of the ground pad wires, and forming electrical connections to the intermediate ground bus at second ends of the ground pad wires,
power straps forming electrical connections to the intermediate power bus at first ends of the power straps, and forming electrical connections to a power mesh at second ends of the power straps, and
ground straps forming electrical connections to the intermediate ground bus at first ends of the ground straps, and forming electrical connections to a ground mesh at second ends of the ground straps.
13. The integrated circuit of claim 12 , wherein a second ring of bonding pads is formed interior to the first ring of bonding pads, and the intermediate power bus and the intermediate ground bus are disposed exterior to the second ring of bonding pads.
14. The integrated circuit of claim 12 , wherein:
a second ring of bonding pads is formed interior to the first ring of bonding pads,
the intermediate power bus and the intermediate ground bus are disposed exterior to the second ring of bonding pads, and
exactly one of one of the power straps and one of the ground straps is disposed between each of the bonding pads of the second ring of bonding pads.
15. An integrated circuit, comprising:
a monolithic semiconducting substrate formed in a chip, the chip having a peripheral edge, a backside, and an opposing top on which circuitry is formed,
a first ring of bonding pads formed in a contiguous pattern completely around the peripheral edge, a plurality of the bonding pads configured as power pads and a plurality of the bonding pads configured as ground pads,
a second ring of bonding pads formed interior to the first ring of bonding pads,
an intermediate power bus disposed interior to the first ring of bonding pads and exterior to the second ring of bonding pads on the chip, the intermediate power bus forming no direct electrical connections to any core devices,
an intermediate ground bus disposed interior to the first ring of bonding pads and exterior to the second ring of bonding pads on the chip, the intermediate ground bus forming no direct electrical connections to any core devices,
power pad wires forming exclusive electrical connections to the power pads at first ends of the power pad wires, and forming electrical connections to the intermediate power bus at second ends of the power pad wires,
ground pad wires forming exclusive electrical connection to the ground pads at first ends of the ground pad wires, and forming electrical connections to the intermediate ground bus at second ends of the ground pad wires,
power straps forming electrical connections to the intermediate power bus at first ends of the power straps, and forming electrical connections to a power mesh at second ends of the power straps,
ground straps forming electrical connections to the intermediate ground bus at first ends of the ground straps, and forming electrical connections to a ground mesh at second ends of the ground straps, and
exactly one of one of the power straps and one of the ground straps is disposed between each of the bonding pads of the second ring of bonding pads.