Method of implementing power-on-reset in power switches
View Patent ↗A power switch circuit and method is provided for having the capability of (1) a power switch circuit having a POR in which the switch is enabled at a predetermined voltage such that the switch is unable to be activated when a minimum lower input voltage is not achieved, to avoid potential conflicts in synchronization and resets with other integrated circuits or chips of an affected system; (2) a POR designed with a delay circuit providing for coordinated stabilization of the power switch before each ON-OFF transition period; (3) using a controlled peaking current in the POR circuit to provide precise RC delay to avoid instability during transition; and (4) a POR providing an externally controlled voltage to power-up other components in the system when energizing of the first component occurs satisfactorily.
1. A power switch circuit comprising:
a power switch including a P-channel Metal Oxide Semiconductor (PMOS) which receives an input voltage, a buffer, and a level-shifter circuit;
a power-on reset (POR) circuit configured for a peaking current technique to generate a current and for generating a power-on reset (POR) signal, wherein the POR circuit comprises two NMOS transistors, four PMOS transistors and three resistors, wherein the two NMOS transistors and the three resistors are configured to generate a small current and utilizing the small current to generate a power-on reset signal when the input voltage reaches two times the threshold voltage of the PMOS;
a delay circuit coupled to the POR circuit, the delay circuit comprising a plurality of the buffer stages, the delay circuit providing an active POR signal;
and an active low reset (PORB) signal for enabling a control loop of the power switch
wherein the active POR signal provides for activating the switch by the PORB signal at a predetermined voltage being at least of a minimum lower input voltage.
2. The power switch circuit of claim 1 , further comprising at least one successive integrated circuit.
3. The power switch circuit of claim 1 , wherein the peaking current technique generates a small current to define a state at a point A of the POR circuit as low, whereinafter when an input voltage reaches two times a threshold voltage, current is provided to change the state of point A from low to high.
4. The power switch circuit of claim 3 , wherein a further delay is inserted into the circuit by charging a capacitor in a predetermined manner.
5. A method of implementing a power-on reset in a power switch circuit to enable the switch at a predefined voltage and to power-up successive integrated circuits, the method comprising:
providing for a power switch including a P-channel Metal Oxide Semiconductor (PMOS) which receives an input voltage, a buffer, and a level-shifter circuit;
providing for a power-on reset (POR) circuit configured for a peaking current technique to generate a current and for generating a power-on reset (POR) signal, wherein the POR circuit comprises two NMOS transistors, four PMOS transistors and three resistors, wherein the two NMOS transistors and the three resistors are configured to generate a small current and utilizing the small current to generate a power-on reset signal when the input voltage reaches two times the threshold voltage of the PMOS;
providing for a delay circuit coupled to the POR circuit, the delay circuit comprising a plurality of the buffer stages, the delay circuit providing an active POR signal;
and providing for an active low reset (PORB) signal for enabling a control loop of the power switch.
6. The method of claim 5 , further comprises the peaking current technique generating a small current to define a state at a point A of the POR circuit as low, whereinafter when an input voltage reaches two times a threshold voltage, providing current and changing the state of point A from low to high.
7. The method of claim 6 , further comprising inserting a further delay into the circuit by charging a capacitor in a predetermined manner.
8. An integrated circuit comprising:
a power switch which receives an input voltage;
a power-on reset (POR) circuit configured for a peaking current technique to generate a current and for generating a power-on reset (POR) signal, wherein the POR circuit comprises two NMOS transistors, four PMOS transistors and three resistors, wherein the two NMOS transistors and the three resistors are configured to generate a small current and utilizing the small current to generate a power-on reset signal when the input voltage reaches two times the threshold voltage of the PMOS;
a delay circuit; coupled to the POR circuit, the delay circuit comprising a plurality of the buffer stages, the delay circuit providing an active POR signal;
one or more successive integrated circuits;
and an active low reset (PORB) signal for enabling a control loop of the power switch,
wherein the active POR signal provides for activating the switch by the PORB signal at a predetermined voltage being at least of a minimum lower input voltage.
9. The integrated circuit of claim 8 , further comprising a plurality of successive integrated circuits.
10. The integrated circuit of claim 9 , wherein the peaking current technique generates a small current to define a state at a point A of the POR circuit as low, whereinafter when an input voltage reaches two times a threshold voltage, current is provided to change the state of point A from low to high.
11. The integrated circuit of claim 10 , wherein in response to a voltage rise of a voltage supply, the circuit generates a signal consistent with a leading part of the POR signal.
12. The integrated circuit of claim 11 , wherein a further delay is inserted into the circuit by charging a capacitor in a predetermined manner.
13. A power switch circuit comprising:
a power switch including a P-channel Metal Oxide Semiconductor (PMOS) which receives an input voltage, a buffer, and a level-shifter circuit;
a power-on reset (POR) circuit configured for a peaking current technique to generate a peaking current and for generating a power-on reset (POR) signal, wherein the POR circuit comprises two NMOS transistors, four PMOS transistors and three resistors, wherein the two NMOS transistors and the three resistors are configured to generate a small current and utilizing the small current to generate a power-on reset signal when the input voltage reaches two times the threshold voltage of the PMOS;
a delay circuit coupled with the POR circuit, the delay circuit including a plurality of buffer stages coupled with a current reference input node (IREF) and a capacitor, wherein the current reference input node (IREF) is configured for receiving a reference current derived from the POR circuit, the delay circuit providing an active POR signal,
and an active low reset (PORB) signal for enabling a control loop of the power switch,
wherein the active POR signal provides for activating the switch by the PORB signal at a predetermined voltage being at least of a minimum lower input voltage.