Stacked die semiconductor package and method of assembly
View Patent ↗A method of manufacturing a plurality of stacked die semiconductor packages, including: attaching a second silicon wafer to a first silicon wafer, wherein the second silicon wafer has a plurality of open vias; attaching a third silicon wafer to the second silicon wafer, wherein the third silicon wafer has a plurality of open vias, and the open vias of the second and third silicon wafers are aligned with one another; etching a bonding material that attaches the wafers from the aligned open vias; filling the aligned open vias with a conductor; forming conductive bumps at open ends of the aligned open vias; back grinding the first silicon wafer; separating the stacked semiconductor dies from each other; attaching the bump end of the stacked semiconductor dies onto a substrate; encapsulating the stacked semiconductor dies and substrate; and singulating the encapsulated assembly.
1. A method of manufacturing a plurality of stacked die semiconductor packages, comprising:
attaching a bottom surface of a second silicon wafer to a top surface of a first silicon wafer, said second silicon wafer having a plurality of unfilled vias and a layer of bonding material at the bottom surface;
attaching a bottom surface of a third silicon wafer to a top surface of the second silicon wafer, said third silicon wafer having a plurality of unfilled vias and a layer of bonding material at the bottom surface, and said unfilled vias of the second and third silicon wafers are aligned with one another;
removing said bonding material from said aligned unfilled vias;
filling said aligned unfilled vias with a conductor;
forming conductive bumps at ends of said aligned vias;
back grinding a bottom surface of said first silicon wafer;
separating said stacked semiconductor dies from each other;
attaching the bump end of said separated stacked semiconductor dies onto a substrate;
encapsulating said separated stacked semiconductor dies and substrate; and
singulating said encapsulated assembly into individual stacked die semiconductor packages.
2. The method of claim 1 , further comprising:
back grinding a bottom surface on at least one of said second and third silicon wafers prior to applying said layer of bonding material.
3. The method of claim 1 , further comprising:
blind etching a top surface on at least one of said second and third silicon wafers prior to applying said layer of bonding material.
4. The method of claim 3 , further comprising:
applying an insulating layer to said blind etched top surface on at least one of said second and third silicon wafers prior to applying said layer of bonding material.
5. The method of claim 4 , further comprising:
applying a metal layer over said insulating layer on at least one of said second and third silicon wafers prior to applying said layer of bonding material.
6. The method of claim 5 , further comprising:
passivating at least one of said second and third silicon wafers prior to applying said layer of bonding material.
7. The method of claim 1 , further comprising:
attaching a bottom surface of a fourth silicon wafer to a top surface of the third silicon wafer, said fourth silicon wafer having a plurality of unfilled vias and a layer of bonding material at the bottom surface, and said unfilled vias of the second, third and fourth silicon wafers are aligned with one another.