Two-step STI formation process

1. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a first isolation region in the semiconductor substrate;

after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source/drain region; and

after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate comprising:

after the step of forming the source/drain region, etching a portion of the source/drain region away from a gate spacer of the MOS device to form a trench; and

forming an inter-layer dielectric (ILD), wherein the ILD extends into the trench to form the second isolation region.

2. The method of claim 1 , wherein the second isolation region has a bottom no higher than a bottom of the source/drain region.

3. The method of claim 1 , wherein the first isolation region adjoins a first side of the source/drain region, and the second isolation region adjoins a second side of the source/drain region.

4. The method of claim 3 , wherein the first side is parallel to a source-to-drain direction of the MOS device, and the second side is perpendicular to the source-to-drain direction of the MOS device.

5. The method of claim 1 further comprising a buried oxide layer underlying and adjoining a bottom surface of the semiconductor substrate, wherein the first and the second isolation regions both contact the buried oxide layer.

6. The method of claim 1 , wherein the semiconductor substrate is a bulk substrate, and wherein the first and the second isolation regions extend into different depths of the semiconductor substrate.

7. The method of claim 1 further comprising:

forming a source/drain silicide region on the source/drain region; and

blanket forming a contact etch stop layer (CESL) between the ILD and the source/drain silicide region, wherein the step of forming the trench is performed after the step of blanket forming the CESL.

8. The method of claim 1 further comprising:

forming a source/drain silicide region on the source/drain region; and

blanket forming a CESL between the ILD and the source/drain silicide region, wherein the step of forming the trench is performed before the step of blanket forming the CESL.

9. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a metal-oxide-semiconductor (MOS) device comprising:

forming a gate stack on a top surface of the semiconductor substrate;

forming a gate spacer on a sidewall of the gate stack;

forming a source/drain region adjacent the gate spacer; and

forming a silicide region on the source/drain region;

etching a portion of the silicide region and a portion of the source/drain region to form a trench, wherein the trench is spaced apart from an outer edge of the gate spacer by a remaining portion of the source/drain region, and wherein the trench extends below a bottom of the source/drain region; and

forming an inter-layer dielectric (ILD) over the MOS device, wherein the ILD extends into the trench to form a shallow trench isolation (STI) region.

10. The method of claim 9 further comprising, before the step of forming the trench, forming a contact etch stop layer (CESL) between the silicide region and the ILD, wherein the step of forming the trench comprises etching a portion of the CESL.

11. The method of claim 9 further comprising, after the step of forming the trench, forming a CESL between the silicide region and the ILD, wherein the CESL extends into the trench.

12. The method of claim 9 , wherein the STI region adjoins a first side of the source/drain region, and wherein the method further comprises forming an additional STI region before the step of forming the MOS device.

13. The method of claim 12 , wherein the additional STI region adjoins a second side of the source/drain region, and wherein the second side is perpendicular to the first side.

14. The method of claim 12 , wherein the STI region and the additional STI region comprise a same dielectric material, and wherein the steps of forming the additional STI region and forming the ILD are performed using different methods.

15. The method of claim 12 , wherein the STI region and the additional STI region comprise different dielectric materials.

16. The method of claim 9 , wherein the STI region extends down to contact a buried oxide layer underlying the semiconductor substrate.

17. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor substrate;

forming a first shallow trench isolation (STI) region in the semiconductor substrate, wherein the first STI region has a first lengthwise direction, and wherein the first STI region adjoins an active region;

forming a first and a second gate electrode strip over the active region and the first STI region, wherein the first and the second gate electrode strips are parallel to each other;

forming a common source/drain region in the active region and between the first and the second gate electrode strips;

forming a silicide region on the common source/drain region;

etching a portion of the silicide region and a portion of the common source/drain region to form a trench, wherein the trench has a second lengthwise direction parallel to the first and the second gate electrode strips; and

forming an inter-layer dielectric (ILD) having a top surface higher than top surfaces of the first and the second gate electrode strips, wherein the ILD extends into the trench to form a second STI region.

18. The method of claim 17 further comprising, before the step of forming the trench, forming a contact etch stop layer (CESL) on the silicide region, wherein the step of forming the trench comprises etching a portion of the CESL.

19. The method of claim 17 further comprising, after the step of forming the trench, forming a CESL on the silicide region, wherein the CESL extends into the trench.