Nonvolatile memory with a current sense amplifier having a precharge circuit and a transfer gate coupled to a sense node
View Patent ↗Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result of the sensing to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, by which current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination of the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of this determination; and a transfer gate coupled to the data latch to supply a latched result to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.
1. A sensing circuit for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus, comprising:
a node;
a precharge circuit coupled to the node for charging the node to an initial voltage;
an intermediate circuit coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell;
a comparator circuit coupled to the node to perform a determination of the conduction current by a rate of discharge at the node;
a data latch coupled to the comparator circuit to hold the result of said determination; and
a transfer gate coupled to the data latch to supply the result latched therein to the data bus independently of the node,
wherein the precharge circuit can be charged up concurrently with supplying the latched result to the data bus.
2. A sensing circuit as in claim 1 , wherein: each memory cell of the group is accessible by an associated bit line; and said intermediate circuit is coupled to the associated bit line.
3. A sensing circuit as in claim 1 wherein the group of nonvolatile memory cells are a portion of a flash EEPROM.
4. A sensing circuit as in claim 3 , wherein the flash EEPROM is of NAND type.
5. A sensing circuit as in claim 1 , wherein individual non-volatile memory cells each contain a charge storage element.
6. A sensing circuit as in claim 5 , wherein the charge storage element is a floating gate.
7. A sensing circuit as in claim 5 , wherein the charge storage element is a dielectric layer.
8. A sensing circuit as in claim 1 , wherein the nonvolatile memory cells are embodied in a memory card.
9. A sensing circuit as in claim 1 , wherein the comparator circuit performs said determination by comparing the conduction current to a reference value.
10. A sensing circuit for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus, comprising:
a node;
a precharge circuit coupled to the node for charging the node to an initial voltage;
an intermediate circuit coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell;
a comparator circuit coupled to the node to perform a determination of the conduction current by a rate of discharge at the node;
a data latch coupled to the comparator circuit to hold the result of said determination; and
a transfer gate coupled to the data latch to supply the result latched therein to the data bus independently of the node,
wherein the result latched in the data latch is supplied to the data bus independently of switching levels in the intermediate circuit.