IP Library Granted Patent US 7,682,974
Granted Patent B2
US 7,682,974 · App. 12/130,537 · Granted Mar 23, 2010

Method for manufacturing semiconductor device

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Quick Facts
Patent No.
US 7,682,974
App. No.
12/130,537
Granted
Mar 23, 2010
Kind
B2
Abstract

A method for manufacturing a semiconductor device includes the steps of: forming an etching layer ( 17 ) formed of silicon on a semiconductor substrate ( 10 ); forming a mask layer ( 20 ) with a pattern on the etching layer ( 17 ), which includes an intermediate layer ( 22 ) as a silicon oxide film and a top layer ( 24 ) as a polysilicon; and etching the etching layer ( 17 ) using the mask layer ( 20 ) as a mask, and eliminating the top layer ( 24 ).

Claims (36)

1. A method for manufacturing a semiconductor device comprising the steps of:

forming an etching layer formed of silicon on a semiconductor substrate;

forming a mask layer with a pattern on the etching layer, the mask layer including an intermediate layer formed of a silicon oxide film and a top layer formed of silicon, wherein the step of forming the mask layer includes the steps of:

layering the intermediate layer and the top layer on the etching layer;

patterning the intermediate layer and the top layer;

forming a cover layer formed of a silicon oxide film on the patterned intermediate layer and the top layer; and

forming side wall layers on side surfaces of the patterned intermediate layer and the patterned top layer by etching an entire surface of the cover layer to expose the top layer; and

etching the etching layer using the mask layer as a mask, and eliminating the top layer, the etching layer etched to form a plurality of word lines.

2. The method for manufacturing a semiconductor device according to claim 1 , further comprising the steps of:

forming a first layer formed of a silicon oxide film and a second layer formed of a silicon nitride film sequentially between each of the plurality of word lines which have been etched; and

eliminating the intermediate layer on the etching layer.

3. The method for manufacturing a semiconductor device according to claim 2 , further comprising the step of forming a silicide metal layer on an upper portion of the plurality of word lines.

4. The method for manufacturing a semiconductor device according to claim 3 , wherein the step of forming the silicide metal layer includes the step of forming a metal layer on the plurality of word lines, and the step of forming the silicide metal layer from the metal layer and the upper portion of the plurality of word lines through a thermal processing.

5. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of patterning the intermediate layer and the top layer includes the steps of:

forming an antireflective film and a photoresist film on the top layer;

patterning the antireflective film and the photoresist film; and

etching the intermediate layer and the top layer using the photoresist film as the mask.

6. A method for manufacturing a semiconductor device comprising the steps of:

forming an etching layer;

forming a mask layer with a pattern on the etching layer, the mask layer including an intermediate layer and a top layer formed of the same element as that used for forming the etching layer, wherein the step of forming the mask layer includes the steps of:

layering the intermediate layer and the top layer on the etching layer;

patterning the intermediate layer and the top layer;

forming a cover layer formed of a silicon oxide film on the patterned intermediate layer and the top layer; and

forming side wall layers on side surfaces of the patterned intermediate layer and the patterned top layer by etching an entire surface of the cover layer to expose the top layer; and

etching the etching layer using the mask layer as a mask, and eliminating the top layer, the etching layer etched to form a plurality of word lines.

7. The method for manufacturing a semiconductor device according to claim 6 , further comprising the steps of:

forming a first layer and a second layer each formed of the same material as that used for forming the intermediate layer between each of the plurality of word lines which have been etched; and

eliminating the intermediate layer on the etching layer.

8. The method for manufacturing a semiconductor device according to claim 1 , wherein the etching layer is a gate layer.

9. The method for manufacturing a semiconductor device according to claim 6 , wherein the etching layer is a gate layer.

10. The method for manufacturing a semiconductor device according to claim 6 , wherein the step of patterning the intermediate layer and the top layer includes the steps of:

forming an antireflective film and a photoresist film on the top layer;

patterning the antireflective film and the photoresist film; and

etching the intermediate layer and the top layer using the photoresist film as the mask.

11. The method for manufacturing a semiconductor device according to claim 1 , wherein the step of forming the cover layer does not form side wall layers.

12. The method for manufacturing a semiconductor device according to claim 6 , wherein the step of forming the cover layer does not form side wall layers.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036043/0013 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2008
From: INOUE, FUMIHIKO; YAMAMOTO, JUNPEI; SASSA, SUGURU
To: SPANSION LLC
Reel/Frame 021550/0349 →