Memory architecture for high throughput RS decoding for MediaFLO receivers
View Patent ↗A system and method for increasing the throughput of a RS decoder in MediaFLO™ receivers. A MAC de-interleaver RAM architecture allowing operation of parallel RS decoders comprises of four equal portioned memory banks, a codeword buffer for data correction, and a higher bit width RAM. The method of increasing throughput of RS decoder by minimizing RAM access and clock frequency includes increasing the bit width of the de-interleaver RAM, using parallel RS decoder cores for decoding received data, partitioning a 4-bank RAM and ECB allocation scheme, and correcting the data using intermediate buffers. The architecture enables on-chip implementation of the MAC de-interleaver RAM and RS decoders with reduced power consumption and provide higher RS decoder throughput.
1. A Reed-Solomon (RS) decoding engine in a memory architecture of a media access control (MAC) de-interleaver random access memory (RAM) that increases a throughput of RS decoders in a MediaFLO™ (forward link only) receiver, the architecture comprising:
parallel RS decoder cores comprising a RS decoder that decodes received data, wherein the number of parallel RS decoders equals a ceiling 16 ms/(122*floor (b/122/6)*r*t), wherein b is the size of a de-interleaver RAM in bytes, t is a clock period, r is a RS decoder core throughput in clock cycles per codeword, 16 is a size of a RS codeword, and 122 is the number of codewords in one error control block (ECB), wherein said number of codewords is equal to the number of bytes in one MAC packet; and
a single port RAM for accessing said de-interleaver RAM.
2. The architecture of claim 1 , wherein said single port for RAM allows arbitration free access of said RS decoder cores and said MAC de-interleaver RAM.
3. The architecture of claim 1 , wherein said RS decoder has a codeword size of 16 bytes.
4. The architecture of claim 1 , wherein the number of RS decoders is in the range from 2 to 8.
5. The architecture of claim 1 , wherein the number of said RS decoders is calculated using:
clock frequency;
total interleaver RAM size; and
RS decoder core throughput.
6. A media access control (MAC) de-interleaver random access memory (RAM) architecture in a MediaFLO™ (forward link only) receiver allowing operation of parallel Reed-Solomon (RS) decoders for higher throughput, the architecture comprising:
four equal partitioned memory banks;
a codeword buffer for data correction; and
a high bit width RAM.
7. The architecture of claim 6 , wherein each of said partitioned memory banks correspond to one frame of data.
8. The architecture of claim 6 , wherein said high data bit width of RAM allows simultaneous processing of data in said parallel RS decoders.
9. The architecture of claim 6 , wherein said high data width reduces the memory access by a factor equal to the number of parallel RS decoder cores.
10. The architecture of claim 6 , further comprising a plurality of said codeword buffers.
11. The architecture of claim 6 , wherein said codeword buffer comprises a RAM.
12. The architecture of claim 6 , wherein said codeword buffer comprises flip-flops.
13. The architecture of claim 6 , wherein said codeword buffer is clocked at twice the clock rate of said RAM.
14. A method of increasing a throughput of a Reed Solomon (RS) decoder in a media access control (MAC) de-interleaver random access memory (RAM) architecture of a MediaFLO™ receiver comprising of RS decoders and codeword buffers, said method comprising:
increasing a bit width of said MAC de-interleaver RAM;
using parallel RS decoder cores for decoding received data;
partitioning said MAC de-interleaver RAM into equal sections for parallel processing of RS codewords; and
using small codeword buffers for data correction.
15. The method of claim 14 , wherein said MAC de-interleaver RAM is portioned into at least four equal RAM banks.
16. The method of claim 14 , wherein said parallel RS decoders process RS codeword data simultaneously from a received superframe.
17. The method of claim 14 , wherein said codeword buffer perform data correction without accessing said MAC de-interleaver RAM.
18. The method of claim 14 , wherein said codeword buffers enable a parallel RS decoder operation.
19. The method of claim 14 , wherein said codeword buffers are duplicated to attain maximum RS decoder throughput.
20. The method of claim 14 , wherein a size of said codeword buffers is maximized to attain a maximum RS decoder throughput.