Techniques for three-dimensional circuit integration
View Patent ↗Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
1. A method of fabricating a three-dimensional integrated circuit, comprising the steps of:
forming a bottom device layer by forming a digital CMOS circuitry layer adjacent to a first substrate and depositing a first bonding oxide layer over a side of the digital CMOS circuitry layer opposite the first substrate;
forming a top device layer by forming an analog CMOS and photonics circuitry layer in a SOI layer adjacent to a second substrate, the SOI layer having a BOX with a thickness of greater than or equal to about one micrometer and depositing a second bonding oxide layer over a side of the analog CMOS and photonics circuitry layer opposite the second substrate;
forming an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer; and
removing the first substrate from the bottom device layer.
2. The method of claim 1 , wherein the digital CMOS circuitry layer comprises a plurality of digital CMOS logic components.
3. The method of claim 1 , wherein the analog CMOS and photonics circuitry layer comprises one or more of analog modulators, analog drivers, analog transimpedance amplifiers, optical waveguides, optical detectors, switches and optical couplers.
4. The method of claim 1 , wherein the BOX has a thickness of greater than or equal to about two micrometers.
5. The method of claim 1 , further comprising the steps of:
forming one or more metal pads on the digital CMOS circuitry layer; and
connecting the metal pads to one or more of the digital CMOS logic components with intra-layer conductive vias.
6. The method of claim 3 , further comprising the steps of:
forming one or more metal pads in the analog CMOS and photonics circuitry layer; and
connecting the metal pads to one or more of the analog modulators, the analog drivers, the analog transimpedance amplifiers, the optical waveguides, the optical detectors, the switches and the optical couplers with intra-layer conductive vias.
7. The method of claim 1 , further comprising the step of:
forming one or more one inter-layer conductive vias interconnecting the top device layer and the bottom device layer.
8. The method of claim 1 , further comprising the step of:
flipping the top device layer so as to permit face-to-face bonding between the bonding oxide layer of the top device layer and the bonding oxide layer of the bottom device layer.
9. The method of claim 1 , wherein the first substrate is removed from the bottom device layer using one or more of grinding, chemical-mechanical polishing and deep reactive ion etching.
10. The method of claim 1 , further comprising the steps of:
providing a semiconductor optical amplifier; and
bonding the semiconductor optical amplifier to the analog CMOS and photonics circuitry layer.
11. The method of claim 10 , wherein the bonding step further comprises the step of:
forming an oxide-to-oxide bond between an oxide layer deposited over the semiconductor optical amplifier and an oxide layer deposited over the analog CMOS and photonics circuitry layer.