Programmable heavy-ion sensing device for accelerated DRAM soft error detection
View Patent ↗Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
1. A Dynamic Random Access Memory (DRAM) array for detecting a Single Event Upset (SEU) event, comprising:
a set of word decoders to drive word lines of the a set of DRAM cells;
a set of sense amplifiers coupled to the set of DRAM cells; and
a bit decoder for multiplexing the set of sense amplifiers;
wherein at least a portion of the DRAM array is operative to detect an SEU event.
2. The DRAM array of claim 1 , further comprising a reference voltage generator for providing a reference voltage to the set of sense amplifiers.
3. The DRAM array of claim 2 , the reference voltage being centered between a logic zero and a logic one in a normal mode.
4. The DRAM array of claim 1 , wherein at least one of the set of sense amplifiers detects the SEU event when a SEU reduces a stored charge in the set of DRAM cells.
5. The DRAM array of claim 4 , wherein the at least one sense amplifier further generates an output of a logic zero when the SEU event is detected.
6. A Dynamic Random Access Memory (DRAM) array for detecting a Single Event Upset (SEU) event, comprising:
a set of word decoders to drive word lines of the a set of DRAM cells;
a set of sense amplifiers coupled to the set of DRAM cells; and
a bit decoder for multiplexing the set of sense amplifiers;
the reference voltage being higher in a soft error detection (SED) mode to reduce an effective critical charge level of a stored logic one in the set of DRAM cells.
7. A Dynamic Random Access Memory (DRAM) array for detecting a Single Event Upset (SEU) event, comprising:
a set of word decoders to drive word lines of the a set of DRAM cells;
a set of sense amplifiers coupled to the set of DRAM cells; and
a bit decoder for multiplexing the set of sense amplifiers;
the DRAM array having an initial value of a logic one, and an SEU event being detected when any of the set of DRAM cells is set to a logic zero based on a reading from the set of sense amplifiers.