Data output circuit
View Patent ↗A data output circuit includes: a data generating circuit configured to generate output data; and a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
1. A data output circuit comprising:
a data generating circuit configured to generate output data; and
a serial output circuit configured to receive an address corresponding to the data generating circuit, hold a parallel data input during a time period over which the address is being received, and serially output the output data generated by the data generating circuit and the held parallel data in accordance with an output direction signal for directing output of the data.
2. The data output circuit according to claim 1 , wherein
the serial output circuit is further configured to: receive the address corresponding to the data generating circuit on the basis of a clock signal; and hold the parallel data input into the serial output circuit on the basis of the clock signal.
3. The data output circuit according to claim 2 , wherein
the serial output circuit includes:
an address circuit configured to
receive the address corresponding to the data generating circuit, and
output an output start signal into the data generating circuit in order to cause the data generating circuit to serially output the output data, when the output direction signal is input; and
a shift output circuit configured to
hold the parallel data as memory data on the basis of the clock signal during a time period over which the address corresponding to the data generating circuit is being input,
add to the memory data the output data serially output from the data generating circuit and shift and serially output the memory data added with the output data on the basis of the clock signal, when the output direction signal is input.
4. The data output circuit according to claim 3 , wherein
the shift output circuit is further configured to
hold an output determining data indicating presence or absence of the output data as a part of the memory data,
add the output data from the data generating circuit to the memory data in such a manner that the output data is output after the parallel data and the output determining data, and shift and serially output the memory data added with the output data on the basis of the clock signal when the output direction signal is input.