IP Library Granted Patent US 8,572,517
Granted Patent B2
US 8,572,517 · App. 12/136,277 · Granted Oct 29, 2013

System and method for modifying a data set of a photomask

Inventors: Dipankar Pramanik (Saratoga, CA); Michiel Victor Paul Kruger (Berkeley, CA); Roy V. Prasad (Los Gatos, CA); Abdurrahman Sezginer (Monte Sereno, CA)
Assignee: Cadence Design Systems, Inc.
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Quick Facts
Patent No.
US 8,572,517
App. No.
12/136,277
Granted
Oct 29, 2013
Kind
B2
Abstract

The present invention provides a method for compensating infidelities of a process that transfers a pattern to a layer of an integrated circuit, by minimizing, with respect to a photomask pattern, a cost function that quantifies the deviation between designed and simulated values of circuit parameters of the pattern formed on a semiconductor wafer.

Claims (34)

1. A method for optical compensation comprising:

using a computer system to create a simulated circuit pattern using a lithography process, wherein the lithography process uses a photomask defined by a data set having a plurality of polygons that define patterns on the photomask;

calculating a cost function based on an electrical parameter of the simulated circuit pattern, wherein the cost function comprises terms defined by at least one of:

(a) a sum of squares of normalized differences between simulated and designed values of electrical parameters for a multitude of circuit components,

(b) an amount by which the simulated value of the electrical parameter exceeds a maximum allowable value,

(c) an amount by which the simulated value of the electrical parameter falls below a minimum allowable value,

(d) the difference of simulated values of a first and a second electrical parameter of a simulated circuit pattern,

(e) a change in the simulated value of the electrical parameter in response to a change in a condition of the lithography process, and

(f) a restricted simulated value of the electrical parameter that is not larger than a maximum allowable value or not smaller than a minimum allowable value,

and wherein the electrical parameter describes an electrical operational characteristic of the simulated circuit pattern; and

adjusting the polygons based on the calculated cost function in order to reduce the value of the cost function.

2. The method of claim 1 , wherein adjusting the polygons comprises at least one of: segmenting an edge of a polygon, altering a polygon by moving a segment of its edge, moving a polygon, adding a polygon to the data set, and removing a polygon from the data set.

3. The method of claim 1 , wherein the electrical parameter comprises one or more parameters from the group consisting of saturation current, leakage current, threshold voltage, gain, resistance, capacitance, and inductance.

4. The method of claim 1 , wherein calculating the cost function further comprises using geometric variables derived from comparing the simulated circuit pattern with a target circuit pattern.

5. The method of claim 1 , further comprising adjusting distribution or polarization variables of the illumination in a pupil of an optical projector in a way to reduce the value of the cost function.

6. The method of claim 1 , wherein the method is performed using a computer program product having computer readable program code functions embedded in a non-transitory computer useable medium.

7. A computer system configured for optical compensation, comprising:

a processor;

a memory connected to the processor; and

a computer-readable medium having instructions embedded therein, the instructions configured to cause the processor to perform the operations of:

creating a simulated circuit pattern using a lithography process, wherein the lithography process uses a photomask defined by a data set having a plurality of polygons that define patterns on the photomask;

calculating a cost function based on an electrical parameter of the simulated circuit pattern, wherein the cost function comprises terms defined by at least one of:

(a) a sum of squares of normalized differences between simulated and designed values of electrical parameters for a multitude of circuit components,

(b) an amount by which the simulated value of the electrical parameter exceeds a maximum permissible value,

(c) an amount by which the simulated value of the electrical parameter falls below a minimum allowable value,

(d) the difference of simulated values of a first and a second electrical parameter of a simulated circuit pattern,

(e) a change in the simulated value of the electrical parameter in response to a change in a condition of the lithography process, and

(f) a restricted simulated value of the electrical parameter that is not larger than a maximum allowable value or not smaller than a minimum allowable value,

and wherein the electrical parameter describes an electrical operational characteristic of the simulated circuit pattern; and

adjusting the polygons based on the calculated cost function in order to reduce the value of the cost function.

8. The system of claim 7 , wherein adjusting the polygons comprises at least one of: segmenting an edge of a polygon, altering a polygon by moving a segment of its edge, moving a polygon, adding a polygon to the data set, and removing a polygon from the data set.

9. The system of claim 7 , wherein the electrical parameter comprises one or more parameters from the group consisting of saturation current, leakage current, threshold voltage, gain, resistance, capacitance, and inductance.

10. The system of claim 7 , wherein calculating the cost function further comprises using geometric variables derived from comparing the simulated circuit pattern with a target circuit pattern.

11. The system of claim 7 , wherein the instructions are further configured to cause the processor to perform the operation of adjusting distribution or polarization variables of the illumination in a pupil of an optical projector in a way to reduce the value of the cost function.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2025
From: CADENCE DESIGN SYSTEMS, INC.
To: SILVACO, INC.
Reel/Frame 070519/0972 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 10, 2008
From: PRAMANIK, DIPANKAR; KRUGER, MICHIEL VICTOR PAUL; PRASAD, ROY V.; SEZGINER, ABDURRAHMAN
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 021071/0922 →
Continuity (1)
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