IP Library Granted Patent US 7,639,166
Granted Patent B2
US 7,639,166 · App. 12/138,236 · Granted Dec 29, 2009

D/A converter circuit

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Quick Facts
Patent No.
US 7,639,166
App. No.
12/138,236
Granted
Dec 29, 2009
Kind
B2
Abstract

A multi-bit D/A converter circuit that prevents a bit inversion and requires a reduced layout area is offered. A first switching circuit is provided in order to select a pair of analog voltages generated across one of resistors in a first resistor string. The selected pair of analog voltages is provided as reference voltages to a second resistor string. A second switching circuit is provided in order to select a pair of analog voltages generated across one of the resistors in the second resistor string. The selected pair of analog voltages is provided as reference voltages to a third resistor string. A third switching circuit is provided in order to select one of analog voltages generated in the third resistor string.

Claims (27)

1. A D/A converter circuit that converts an input digital signal comprising a plurality of upper bits and a plurality of lower bits into an analog voltage, comprising:

a first resistor string that comprises a plurality of first resistors connected in series and generates a plurality of first analog voltages;

a first switching circuit that selects a pair of first analog voltages out of the first analog voltages generated by the first resistor string according to the upper bits;

a second resistor string that comprises a plurality of second resistors connected in series, is provided with the pair of first analog voltages as reference voltages and generates a plurality of second analog voltages; and

a second switching circuit that selects a pair of second analog voltages out of the second analog voltages generated by the second resistor string according to the lower bits,

wherein the selected pair of the first analog voltages is provided to the second resistor string without passing through a buffer, and

a resistance of the second resistors is larger than a resistance of the first resistors.

2. The D/A converter circuit of claim 1 , wherein the first switching circuit is configured to supply, in one instance, a first analog voltage generated at one end of one first resistor to the second resistor string as a first reference voltage and another first analog voltage generated at another end of said one first resistor that is lower than the first analog voltage supplied as the first reference voltage to the second resistor string as a second reference voltage.

3. A D/A converter circuit of that converts an input digital signal comprising a plurality of upper bits and a plurality of lower bits into an analog voltage, comprising:

a first resistor string that comprises a plurality of first resistors connected in series and generates a plurality of first analog voltages;

a first switching circuit that selects a pair of first analog voltages out of the first analog voltages generated by the first resistor string according to the upper bits;

a second resistor string that comprises a plurality of second resistors connected in series, is provided with the pair of first analog voltages as reference voltages and generates a plurality of second analog voltages; and

a second switching circuit that selects a pair of second analog voltages out of the second analog voltages generated by the second resistor string according to the lower bits,

wherein the first switching circuit is configured to supply, in one instance, a first analog voltage generated at one end of one first resistor to the second resistor string as a first reference voltage and another first analog voltage generated at another end of said one first resistor that is lower than the first analog voltage supplied as the first reference voltage to the second resistor string as a second reference voltage, and

the first switching circuit is configured to supply, in another instance, a first analog voltage generated at one end of another first resistor to the second resistor string as the first reference voltage and another first analog voltage generated at another end of said another first resistor that is higher than the first analog voltage supplied as the first reference voltage in said another instance to the second resistor string as the second reference voltage.

4. A D/A converter circuit that converts an input digital signal comprising a plurality of upper bits and a plurality of lower bits into an analog voltage, comprising:

a first resistor string that comprises a plurality of first resistors connected in series and generates a plurality of first analog voltages;

a first switching circuit that selects a pair of first analog voltages out of the first analog voltages generated by the first resistor string according to the upper bits;

a second resistor string that comprises a plurality of second resistors connected in series, is provided with the pair of first analog voltages as reference voltages and generates a plurality of second analog voltages; and

a second switching circuit that selects a pair of second analog voltages out of the second analog voltages generated by the second resistor string according to the lower bits,

wherein the first switching circuit is configured to supply a first analog voltage generated at one end of two consecutive first resistors connected in series to the second resistor string as a first reference voltage and another first analog voltage generated at another end of the two consecutive first resistors connected in series to the second resistor string as a second reference voltage.

5. A D/A converter circuit that converts an input digital signal comprising a plurality of upper bits and a plurality of lower bits into an analog voltage, comprising:

a first resistor string that comprises a plurality of first resistors connected in series and generates a plurality of first analog voltages;

a first switching circuit that selects a pair of first analog voltages out of the first analog voltages generated by the first resistor string according to the upper bits;

a second resistor string that comprises a plurality of second resistors connected in series, is provided with the pair of first analog voltages as reference voltages and generates a plurality of second analog voltages; and

a second switching circuit that selects a pair of second analog voltages out of the second analog voltages generated by the second resistor string according to the lower bits,

wherein the first switching circuit selects a pair of first analog voltages generated at both ends of two consecutive first resistors connected in series, and the second resistor string further comprises an adjusting resistor connected in series with the second resistors to adjust an abrupt change caused in the analog output voltage in response to the digital input signal.

Assignments (9)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064070/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Aug 25, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 039853/0001 →
SECURITY INTEREST Recorded Apr 15, 2016
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH
Reel/Frame 038620/0087 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 033813 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jan 21, 2015
From: SYSTEM SOLUTIONS CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 034816/0510 →
CHANGE OF NAME Recorded Dec 3, 2014
From: SANYO SEMICONDUCTOR CO., LTD
To: SYSTEM SOLUTIONS CO., LTD.
Reel/Frame 034537/0044 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 24, 2014
From: SANYO SEMICONDUCTOR CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 033813/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT #12/577882 PREVIOUSLY RECORDED ON REEL 026594 FRAME 0385. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 6, 2014
From: SANYO ELECTRIC CO., LTD
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 032836/0342 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2011
From: SANYO ELECTRIC CO., LTD.
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 026594/0385 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2008
From: IIJIMA, TAKASHI
To: SANYO ELECTRIC CO., LTD.; SANYO SEMICONDUCTOR CO., LTD.
Reel/Frame 021473/0891 →