VERTICAL TRANSISTOR WITH INTEGRATED ISOLATION
A vertical transistor with integrated isolation is provided. The vertical transistor includes a vertical semiconductor structure and an isolation layer on a bottom surface of the vertical semiconductor structure. The vertical transistor further includes a plurality of terminals on a top surface of the vertical semiconductor structure.
1 . A vertical transistor structure comprising:
a vertical semiconductor structure;
an isolation layer on a bottom surface of the vertical semiconductor structure; and
a plurality of terminals on a top surface of the vertical semiconductor structure.
2 . A vertical transistor structure in accordance with claim 1 wherein the isolation layer comprises an electrically isolating material.
3 . A vertical transistor structure in accordance with claim 1 wherein the isolation layer comprises a thermally conducting material.
4 . A vertical transistor structure in accordance with claim 1 wherein the isolation layer comprises silicon dioxide.
5 . A vertical transistor structure in accordance with claim 1 wherein the isolation layer is formed as part of the vertical semiconductor structure.
6 . A vertical transistor structure in accordance with claim 1 wherein the vertical semiconductor structure defines a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET).
7 . A vertical transistor structure in accordance with claim 1 wherein the vertical semiconductor structure defines a Bipolar Junction Transistor (BJT).
8 . A vertical transistor structure in accordance with claim 1 wherein the isolation layer comprises a silicon material.
9 . A vertical transistor structure in accordance with claim 1 wherein the plurality of terminals are configured to be wire bonded to leads of a package.
10 . A power transistor comprising:
a semiconductor chip having a top surface and a bottom surface;
a plurality of terminals on the top surface; and
an integrated isolation region on the bottom surface.
11 . A power transistor in accordance with claim 10 wherein the plurality of terminals are configured to connect to leads of a transistor package.
12 . A power transistor in accordance with claim 10 wherein the integrated isolation region is configured to be mounted directly to a metal flange of a transistor package.
13 . A power transistor in accordance with claim 10 wherein the integrated isolation region comprises silicon dioxide.
14 . A power transistor in accordance with claim 10 wherein the semiconductor chip is configured to be mounted to a non-insulating transistor package.
15 . A power transistor in accordance with claim 10 wherein the semiconductor chip comprises one of a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) and a Bipolar Junction Transistor (BJT).
16 . A power transistor in accordance with claim 10 wherein the semiconductor chip comprise a vertical structure.
17 . A power transistor in accordance with claim 10 wherein the semiconductor chip comprises a radio frequency (RF) device.
18 . A method of fabricating a vertical transistor structure, the method comprising:
forming a plurality of terminals on a top surface of a semiconductor chip; and
forming an integrated isolation layer on a bottom surface of the semiconductor chip such that electrical current flowing vertically downward from at least one of the plurality of terminals is blocked and directed vertically upward to another one of the plurality of terminals.
19 . A method in accordance with claim 18 further comprising forming the integrated isolation layer from silicon dioxide.
20 . A method in accordance with claim 18 further comprising forming the integrated isolation later from a thermally conducting material.