CHIP PACKAGE FOR SEMICONDUCTOR DEVICES
A chip package for semiconductor devices is provided. The chip package includes a flange configured to mount thereon a semiconductor device. The chip package further includes an inverted bridge lead frame above the flange and having a recessed area below a top portion. The inverted bridge lead frame provides semiconductor device terminal connections to at least one lead.
1 . A chip package comprising:
a flange configured to mount thereon a semiconductor device;
a frame mounted on said flange; and
an inverted bridge lead frame mounted on said frame and positioned above the flange and having a recessed area below a top portion, the inverted bridge lead frame providing semiconductor device terminal connections to at least one lead, wherein said inverted bridge lead frame does not directly contact said flange.
2 . A chip package in accordance with claim 1 wherein the recessed area comprises lower connection portions and the inverted bridge lead frame further comprises angled portions between the top portion and the lower connection portions.
3 . A chip package in accordance with claim 1 wherein the inverted bridge lead frame is configured to provide lead connections at different levels.
4 . A chip package in accordance with claim 1 wherein the inverted bridge lead frame comprises an opening configured to receive therethrough the semiconductor device.
5 . A chip package in accordance with claim 1 wherein the flange is non-insulated.
6 . A chip package in accordance with claim 1 wherein the semiconductor device comprises a transistor having a drain, a gate and a source and wherein the top portion of the inverted bridge lead frame is configured to connect to drain and gate wires and the recessed area is configured to connect to source wires.
7 . A chip package in accordance with claim 1 wherein the inverted bridge lead frame comprises a source portion comprising two leads connected to the recessed area.
8 . A chip package in accordance with claim 7 wherein source wire bonds connect to the recessed area.
9 . A chip package in accordance with claim 1 wherein terminal wires extend in the same direction from the top portion and the recessed area.
10 . A chip package in accordance with claim 1 wherein the semiconductor device comprises a vertical structure transistor.
11 . A chip package in accordance with claim 1 , wherein the inverted bridge lead frame is supported by the frame.
12 . A chip package in accordance with claim 11 wherein the flange, frame and inverted bridge lead frame are configured in a standard footprint.
13 . A lead frame for a chip package, the lead frame comprising:
a planar top portion having a plurality of leads; and
a recessed area having a lower connection portion, the lower connection portion in a parallel and lower plane to the planar top portion, wherein said plurality of leads of said top portion and said lower connection portion comprise connection terminals that extend in the same direction.
14 . A lead frame in accordance with claim 13 further comprising a source portion having the recessed area and comprising a plurality of source leads.
15 . A lead frame in accordance with claim 14 wherein the planar top portion comprises at least one drain lead and at least one gate lead.
16 . A lead frame in accordance with claim 13 further comprising angled portions extending downward from the planar top portion to the lower connection portion.
17 . A lead frame in accordance with claim 16 wherein the angled portions are inwardly angled.
18 . A lead frame in accordance with claim 13 wherein the lower connection portion comprises planar connection regions.
19 . A lead frame in accordance with claim 13 wherein the recessed area comprises an opening.
20 . A method for packaging a semiconductor device, the method comprising:
mounting a semiconductor transistor device to a flange;
mounting a frame to said flange; and
connecting terminals of the semiconductor transistor device to an inverted bridge lead frame, wherein (i) said inverted bridge lead frame is mounted on said frame and positioned above said flange, and (ii) said inverted bridge lead frame does not directly contact said flange, (iii) source terminal connections of said semiconductor transistor are below both drain and gate terminal connections.