IP Library Granted Patent US 8,423,705
Granted Patent B2
US 8,423,705 · App. 12/139,274 · Granted Apr 16, 2013

Semiconductor device and method for controlling thereof

Inventors: Hirokazu Nagashima (Kawasaki, JP); Kazuki Yamauchi (Kawasaki, JP); Junya Kawamata (Kawasaki, JP); Tsutomu Nakai (Kawasaki, JP); Kenji Arai (Kawasaki, JP); Kenichi Takehana (Kawasaki, JP)
Assignee: Spansion LLC
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Quick Facts
Patent No.
US 8,423,705
App. No.
12/139,274
Granted
Apr 16, 2013
Kind
B2
Abstract

A semiconductor device includes a first nonvolatile storage area including a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, and a control portion selecting one of a first mode and a second mode. In first mode, sectors where the third nonvolatile storage area is not located in the first nonvolatile storage area are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area. In the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.

Claims (18)

1. A semiconductor device comprising:

a first nonvolatile storage area including a plurality of sectors;

a second nonvolatile storage area;

a third nonvolatile storage area located in the first nonvolatile storage area;

a fourth nonvolatile storage area located in the second nonvolatile storage area; and

a control portion that is configured to select between two modes that control storage in four storage areas selecting one of a first mode and a second mode wherein the first and the second modes determine whether control information is stored in the third or the fourth nonvolatile storage area wherein one of the first mode and the second mode is a boot mode and in the first mode the third storage area is used as one time programmable memory, wherein:

in the first mode, sectors of the first nonvolatile storage area where the third nonvolatile storage area is not located are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area; and

in the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.

2. The semiconductor device according to claim 1 , wherein the first nonvolatile storage area is larger than the second nonvolatile storage area.

3. The semiconductor device according to claim 1 , wherein a storage area of the second nonvolatile storage area other than another storage area in which the fourth nonvolatile storage area is provided is unused in the second mode.

4. The semiconductor device according to claim 1 , wherein the first nonvolatile storage area and the second nonvolatile storage area have an identical number of columns, and the control portion erases data stored in the first nonvolatile storage area and data in the second nonvolatile storage area simultaneously for each column.

5. The semiconductor device according to claim 4 , wherein the third nonvolatile storage area and the fourth nonvolatile storage area are located in an identical column.

6. The semiconductor device according to claim 1 , wherein the third nonvolatile storage area and the fourth nonvolatile storage area are one time memories.

7. The semiconductor device according to claim 1 , wherein the control portion inhibits one of the first mode and the second mode from being reselected once any one of the first mode and the second mode is selected.

8. A method for controlling a semiconductor device including a first nonvolatile storage area containing a plurality of sectors, a second nonvolatile storage area, a third nonvolatile storage area located in the first nonvolatile storage area, a fourth nonvolatile storage area located in the second nonvolatile storage area, comprising:

from a controller that is configured to select between two modes that control storage in four storage areas, selecting one of a first mode and a second mode wherein the first and the second modes determine whether control information is stored in the third or the fourth nonvolatile storage area wherein one of the first mode and the second mode is a boot mode and in the first mode the third storage area is used as one time programmable memory, wherein:

in the first mode, sectors of the first nonvolatile storage area where the third nonvolatile storage area is not located are used as a main storage area, and the second nonvolatile storage area is used to store a program or data that is read before the first nonvolatile storage area is accessed, the third nonvolatile storage area being used to store control information that controls writing, reading, and erasing of data involved in the first nonvolatile storage area or the second nonvolatile storage area; and

in the second mode, the first nonvolatile storage area is used as the main storage area, and the fourth nonvolatile storage area is used to store the control information.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036055/0276 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Dec 30, 2014
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 034715/0305 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2008
From: NAGASHIMA, HIROKAZU; YAMAUCHI, KAZUKI; KAWAMATA, JUNYA; NAKAI, TSUTOMU; ARAI, KENJI; TAKEHANA, KENICHI
To: SPANSION LLC
Reel/Frame 021483/0774 →
Priority Claims (1)
JP 2007-159566 · Jun 15, 2007 · national
Continuity (1)
Related Publication 20080320208A1 · Dec 25, 2008