Method of evaluating thermal stress resistance of semiconductor device, and semiconductor wafer having test element
View Patent ↗A thermal stress resistance evaluating method of a semiconductor device includes: forming a test circuit on a corner of each of unit regions arranged on a wafer in an array arrangement; forming a TEG chip by dicing a TEG chip region which is determined by grouping at least two of the unit regions in a predetermined shape; assembling a packaged TEG chip from the TEG chip; and executing a temperature cycling test on the packaged TEG chip by using the test circuit on the TEG chip. According to such a configuration, by adjusting the predetermined shape, the packaged TEG chip of various sizes can be formed in accordance with the design of the product chip size.
1. A semiconductor wafer comprising:
a substrate;
a plurality of test elements formed on the substrate;
a plurality of unit chips on each of which a first test element of the plurality of test elements is formed and each of which is able to be assembled to form a packaged TEG chip to be evaluated; and
a scribe line configured to surround each of the plurality of unit chips and on which a second test element of the plurality of test elements having a same circuit configuration to the first test element.
2. The semiconductor wafer according to claim 1 , wherein a plurality of selected test elements of the plurality of test elements are arranged in a predetermined direction and formed on a first unit chip of the plurality of unit chips, on a second unit chip of the plurality of unit chips arranged in adjacent to the first unit chip via the scribe line, and on the scribe line arranged between the first unit chip and the second unit chip.
3. The semiconductor wafer according to claim 2 , wherein the plurality of selected test elements are arranged in the predetermined direction at a constant pitch.
4. The semiconductor wafer according to claim 3 , wherein the plurality of unit chips are same to each other in size.
5. A manufacturing method of a semiconductor product comprising:
providing a semiconductor wafer according to claim 1 ;
forming a first test chip composed of two or more of the plurality of unit chips by dicing the semiconductor wafer; and
assembling a packaged TEG chip from the first test chip.
6. The manufacturing method according to claim 5 , further comprising:
composing a second test chip composed of a different number of the plurality of unit chips to the first test chip and two or more of the plurality of unit chips by dicing the semiconductor wafer on which the first test chip is formed.