Memory device with a selection element and a control line in a substantially similar layer
View Patent ↗The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.
1. A method of making a memory device with a selection element and a control line in a layer of the memory device, comprising:
forming a first layer with a first control line;
forming a memory element coupled to the first control line;
forming a metal via coupled to the memory element;
forming a second layer with a selection element coupled the metal via; and
forming a wordline in the second layer, the wordline coupled to the selection element.
2. The method of claim 1 , the selection element is a diode.
3. The method of claim 2 , the diode comprises a p-n junction diode.
4. The method of claim 2 , the diode is a Schottky diode.
5. The method of claim 2 , the diode is a zener diode.
6. The method of claim 1 , the first control line is a wordline.
7. The method of claim 1 , the first control line is a bitline.
8. The method of claim 1 , the selection element possesses switching characteristics to write, read and erase the memory device.
9. The method of claim 1 , the selection element abuts the wordline.
10. A method of making a memory device with a selection diode in the same layer as a wordline comprising:
forming a first layer comprising a bitline;
depositing a first interlayer dielectric stack upon the first layer;
forming a via opening in the first dielectric stack;
forming a memory element at the bottom of the via opening, the memory element coupled to the bitline;
filling the via opening with a conductor;
polishing the conductor to form a via plug;
depositing a second dielectric stack;
masking, exposing, and etching a first region of the second dielectric stack;
depositing a semiconductor in the first region of the second dielectric stack;
masking and implanting a p-doped portion of the semiconductor;
masking and implanting an n-doped portion of the semiconductor, the n-dope portion abutting the p-doped portion;
annealing the p-doped and n-doped portions of the semiconductor;
masking, exposing and etching a second region of the second dielectric stack, the second region abutting the p-doped portion of the semiconductor;
depositing a barrier metal and copper in the second region to form a wordline; and
polishing the wordline.
11. The method of claim 10 , the n-doped portion and p-doped portion of the semiconductor forms a p-n junction diode.
12. The method of claim 10 , the n-doped portion and p-doped portion of the semiconductor forms a zener diode.
13. The method of claim 10 , the n-doped portion and p-doped portion of the semiconductor forms a Schottky diode.
14. The method of claim 10 , the semiconductor is one of Germanium, Silicon and a III-V compound.
15. The method of claim 10 , the conductor is one of Cu, W, Al, Ti and Ta.
16. The method of claim 10 , the selection diode abuts the word line.
17. The method of claim 10 , the p-doped region of the selection diode abuts the wordline.
18. The method of claim 10 , the selection diode possesses switching characteristics to write, read and erase the memory element.
19. The method of claim 10 , further coupling the bitline to a voltage source.
20. The method of claim 10 , further coupling the wordline to a voltage source.