Semiconductor with through-substrate interconnect
Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
1. A method of fabricating a semiconductor device comprising:
etching a via into a silicon substrate from a first side toward a second side of the silicon substrate;
forming a conductive interconnect in the etched via by filling the via with a metal material, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate;
insulating the conductive interconnect with a dielectric material proximate the first side of the silicon substrate;
forming a metal routing structure on the dielectric material, the metal routing structure being at least partially in the dielectric material; and
removing material from the second side of the semiconductor substrate to expose the second end of the conductive interconnect; wherein:
the metal routing structure is a first metal routing structure;
the dielectric material is a first dielectric material;
the method further includes:
insulating the conductive interconnect and the first metal routing structure with a second dielectric material;
forming a plurality of openings in the second dielectric material, the openings including a first opening generally corresponding to the first metal routing structure, a second opening generally corresponding to the conductive interconnect, and a third opening generally corresponding to a second metal routing structure; and
filling the plurality of openings with a conductive material, thereby forming a first conductive path between the first and second metal routing structures, a second conductive path between the second metal routing structure and the conductive interconnect, and the second metal routing structure.
2. The method of claim 1 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate and on the fabricated transistor;
forming a contact extending through the insulating material to the transistor; and
etching the via includes etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor.
3. The method of claim 1 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate with the fabricated transistor;
forming a contact extending through the insulating material to the transistor, the contact having a first end proximate the gate and source/drain implant regions of the transistor and a second end opposite the first end;
etching the via includes etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor; and
forming the metal routing structure includes:
forming an opening in the dielectric material, the opening exposing the second end of the contact and being laterally spaced apart from the via; and
filling the opening with a conductive material.
4. The method of claim 1 wherein forming the conductive interconnect includes:
forming an insulating material in the etched via;
forming a metal seed material on the insulating material;
blocking selected regions of the seed material located outside of the via with a photoresist; and
plating exposed regions of the seed material to fill the via with a conductive material, thereby forming the conductive interconnect.
5. The method of claim 1 , further comprising forming a conductive redistribution structure proximate the second side of the silicon substrate after exposing the second end of the conductive interconnect, the conductive redistribution structure being in electrical communication with the conductive interconnect.
6. The method of claim 1 wherein the second opening includes a plurality of openings generally corresponding to the conductive interconnect.
7. The method of claim 1 wherein the first metal routing structure is laterally spaced apart from the conductive interconnect.
8. A method of fabricating a semiconductor device comprising:
etching a via into a silicon substrate from a first side toward a second side of the silicon substrate;
forming a conductive interconnect in the etched via, the conductive interconnect having a first end proximate the first side of the silicon substrate and a second end proximate the second side of the silicon substrate;
insulating the conductive interconnect with a first dielectric material proximate the first side of the silicon substrate;
forming a first metal routing structure on the first dielectric material, the first metal routing structure being at least partially in the first dielectric material;
insulating the first metal routing structure with a second dielectric material;
forming first, second, and third openings in the second dielectric material, the first opening generally corresponding to the first metal routing structure, the second opening generally corresponding to the conductive interconnect, and the third opening generally corresponding to a second metal routing structure;
filling the first, second, and third openings with a conductive material, thereby forming a first conductive path between the first and second metal routing structures, a second conductive path between the second metal routing structure and the conductive interconnect, and the second metal routing structure; and
removing material from the second side of the semiconductor substrate to expose the second end of the conductive interconnect.
9. The method of claim 8 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate and on the fabricated transistor;
forming a contact extending through the insulating material to the transistor; and
etching the via includes etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor.
10. The method of claim 1 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate and on the fabricated transistor;
forming a contact extending through the insulating material to the transistor, the contact having a first end proximate the gate and source/drain implant regions of the transistor and a second end opposite the first end;
etching the via includes etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor; and
forming the first metal routing structure includes:
forming an opening in the dielectric material, the opening exposing the second end of the contact and being laterally spaced apart from the via; and
filling the opening with a conductive material.
11. The method of claim 8 wherein forming the conductive interconnect includes:
forming an insulating material in the etched via;
forming a metal seed material on the insulating material;
blocking selected regions of the seed material located outside of the via with a photoresist; and
plating exposed regions of the seed material to fill the via with a conductive material, thereby forming the conductive interconnect.
12. The method of claim 8 , further comprising forming a conductive redistribution structure proximate the second side of the silicon substrate after exposing the second end of the conductive interconnect, the conductive redistribution structure being in electrical communication with the conductive interconnect.
13. A method of fabricating a semiconductor device comprising:
forming a conductive interconnect in a silicon substrate, the conductive interconnect having a first end proximate a first side of the silicon substrate and a second end proximate a second side of the silicon substrate;
forming a first dielectric material on the conductive interconnect proximate the first side of the silicon substrate;
forming a first metal routing structure on the first dielectric material, the first metal routing structure being at least partially in the first dielectric material;
insulating the first metal routing structure with a second dielectric material;
forming first, second, and third openings in the second dielectric material, the first opening generally corresponding to the first metal routing structure, the second opening generally corresponding to the conductive interconnect, and the third opening generally corresponding to a second metal routing structure;
filling the first, second, and third openings with a conductive material, thereby forming a first conductive path between the first and second metal routing structures, a second conductive path between the second metal routing structure and the conductive interconnect, and the second metal routing structure; and
removing material from the second side of the semiconductor substrate to expose the second end of the conductive interconnect.
14. The method of claim 13 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate and on the fabricated transistor;
forming a contact extending through the insulating material to the transistor; and
etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor.
15. The method of claim 13 wherein:
the method further includes:
fabricating a transistor having a gate and source/drain implant regions in the silicon substrate;
forming an insulating material on the silicon substrate and on the fabricated transistor;
forming a contact extending through the insulating material to the transistor, the contact having a first end proximate the gate and source/drain implant regions of the transistor and a second end opposite the first end;
etching a via through the dielectric material and into the silicon substrate laterally adjacent to the transistor, the via extending deeper into the silicon substrate than the source/drain implant regions of the transistor; and
forming the first metal routing structure includes:
forming an opening in the dielectric material, the opening exposing the second end of the contact and being laterally spaced apart from the via; and
filling the opening with a conductive material.
16. The method of claim 13 wherein forming the conductive interconnect includes:
etching a via into the silicon substrate from the first side toward the second side of the silicon substrate;
forming an insulating material in the etched via;
forming a metal seed material on the insulating material;
blocking selected regions of the seed material located outside of the via with a photoresist; and
plating exposed regions of the seed material to fill the via with a conductive material, thereby forming the conductive interconnect.
17. The method of claim 13 , further comprising forming a conductive redistribution structure proximate the second side of the silicon substrate after exposing the second end of the conductive interconnect, the conductive redistribution structure being in electrical communication with the conductive interconnect.